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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-27 14:25:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-27 14:25:34 -0700 |
| commit | d86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd (patch) | |
| tree | 323490f997d9daabaf7d1d1333ee85b50405d8bb /parse-opcodes | |
| parent | 771cd8afc10b438c1e7e8109287d40cb6bd3eddb (diff) | |
| download | riscv-opcodes-d86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd.zip riscv-opcodes-d86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd.tar.gz riscv-opcodes-d86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd.tar.bz2 | |
Separate page faults from physical memory access exceptions
Diffstat (limited to 'parse-opcodes')
| -rwxr-xr-x | parse-opcodes | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/parse-opcodes b/parse-opcodes index 0b375b3..58ebcef 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -33,17 +33,20 @@ arglut['vseglen'] = (31,29) causes = [ (0x00, 'misaligned fetch'), - (0x01, 'fault fetch'), + (0x01, 'fetch access'), (0x02, 'illegal instruction'), (0x03, 'breakpoint'), (0x04, 'misaligned load'), - (0x05, 'fault load'), + (0x05, 'load access'), (0x06, 'misaligned store'), - (0x07, 'fault store'), + (0x07, 'store access'), (0x08, 'user_ecall'), (0x09, 'supervisor_ecall'), (0x0A, 'hypervisor_ecall'), (0x0B, 'machine_ecall'), + (0x0C, 'fetch page fault'), + (0x0D, 'load page fault'), + (0x0F, 'store page fault'), ] csrs = [ |