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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 21:09:14 -0700 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 21:09:14 -0700 |
commit | c0fd7c19a9ade560dbae1d04a8bee19deaca0c1f (patch) | |
tree | c238e1a9484517fc85b2e8a34eaa157fd6a82c72 /parse-opcodes | |
parent | ff4cdc131da26fdd3f0e2e2ec04127e2b55aa4eb (diff) | |
download | riscv-opcodes-c0fd7c19a9ade560dbae1d04a8bee19deaca0c1f.zip riscv-opcodes-c0fd7c19a9ade560dbae1d04a8bee19deaca0c1f.tar.gz riscv-opcodes-c0fd7c19a9ade560dbae1d04a8bee19deaca0c1f.tar.bz2 |
[sim,xcc] removed sll32/srl32/sra32 opcodes
These instructions handled static shift amounts >= 32. Since we have
a 6-bit shift amount field, these opcodes are no longer necessary.
Diffstat (limited to 'parse-opcodes')
-rwxr-xr-x | parse-opcodes | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/parse-opcodes b/parse-opcodes index e9d0249..9d5d539 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -14,7 +14,8 @@ args['rc'] = (4,0) args['imm27'] = (26,0) args['imm20'] = (19,0) args['imm'] = (11,0) -args['shamt'] = (9,5) +args['shamt'] = (10,5) +args['shamtw'] = (9,5) args['fmt'] = (9,5) def binary(n, digits=0): |