diff options
| author | Tim Newsome <tim@sifive.com> | 2016-08-25 13:53:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-25 13:53:21 -0700 |
| commit | 1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658 (patch) | |
| tree | f490e34e1620de350827781653085b7daa9be431 /parse-opcodes | |
| parent | 16c63f381f1e5318fa3edcff9facb7166332a151 (diff) | |
| download | riscv-opcodes-1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658.zip riscv-opcodes-1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658.tar.gz riscv-opcodes-1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658.tar.bz2 | |
Make hardware triggers match latest spec.
Diffstat (limited to 'parse-opcodes')
| -rwxr-xr-x | parse-opcodes | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/parse-opcodes b/parse-opcodes index 44a22da..ba32f6a 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -92,10 +92,10 @@ csrs = [ (0x704, 'mscycle_delta'), (0x705, 'mstime_delta'), (0x706, 'msinstret_delta'), - (0x7a0, 'tdrselect'), - (0x7a1, 'tdrdata1'), - (0x7a2, 'tdrdata2'), - (0x7a3, 'tdrdata3'), + (0x7a0, 'tselect'), + (0x7a1, 'tdata0'), + (0x7a2, 'tdata1'), + (0x7a3, 'tdata2'), (0x7b0, 'dcsr'), (0x7b1, 'dpc'), (0x7b2, 'dscratch'), |