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| author | Tim Newsome <tim@sifive.com> | 2016-06-01 13:16:29 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2016-06-01 13:16:29 -0700 |
| commit | 1783043af1d4af65914f5ff2e167202abb7576c0 (patch) | |
| tree | e385aba35270f45a693126667123a33d218f3411 /parse-opcodes | |
| parent | c8bea5d3b61b04381221398f4085e34281a788b6 (diff) | |
| download | riscv-opcodes-1783043af1d4af65914f5ff2e167202abb7576c0.zip riscv-opcodes-1783043af1d4af65914f5ff2e167202abb7576c0.tar.gz riscv-opcodes-1783043af1d4af65914f5ff2e167202abb7576c0.tar.bz2 | |
Add dret instruction and debug CSRs. (#5)
Diffstat (limited to 'parse-opcodes')
| -rwxr-xr-x | parse-opcodes | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/parse-opcodes b/parse-opcodes index 04bf70f..66fcd73 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -93,6 +93,9 @@ csrs = [ (0x704, 'mscycle_delta'), (0x705, 'mstime_delta'), (0x706, 'msinstret_delta'), + (0x7b0, 'dcsr'), + (0x7b1, 'dpc'), + (0x7b2, 'dscratch'), # Standard Machine RO (0xF00, 'mcycle'), |