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| author | Andrew Waterman <andrew@sifive.com> | 2020-11-20 18:07:19 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-11-20 18:07:19 -0800 |
| commit | bddde8ac4c4f1244a432958c4783f5451b06467d (patch) | |
| tree | bf930a1e71c7515fe54be8f50598930a72b5fbef /opcodes-rv64b | |
| parent | 2b4a0fb477e22e962a8682a57a5e8f18e6e9dc94 (diff) | |
| download | riscv-opcodes-bddde8ac4c4f1244a432958c4783f5451b06467d.zip riscv-opcodes-bddde8ac4c4f1244a432958c4783f5451b06467d.tar.gz riscv-opcodes-bddde8ac4c4f1244a432958c4783f5451b06467d.tar.bz2 | |
Remove instructions already removed from RV64B
Diffstat (limited to 'opcodes-rv64b')
| -rw-r--r-- | opcodes-rv64b | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/opcodes-rv64b b/opcodes-rv64b index 59d0172..58b50ee 100644 --- a/opcodes-rv64b +++ b/opcodes-rv64b @@ -7,11 +7,8 @@ crc32c.d rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3 bmator rd rs1 rs2 31..25=4 14..12=3 6..2=0x0C 1..0=3 bmatxor rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3 -addiwu rd rs1 imm12 14..12=4 6..2=0x06 1..0=3 slliu.w rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 -addwu rd rs1 rs2 31..25=5 14..12=0 6..2=0x0E 1..0=3 -subwu rd rs1 rs2 31..25=37 14..12=0 6..2=0x0E 1..0=3 addu.w rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 @@ -48,10 +45,6 @@ sh1addu.w rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 sh2addu.w rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 sh3addu.w rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 -clmulw rd rs1 rs2 31..25=5 14..12=1 6..2=0x0E 1..0=3 -clmulrw rd rs1 rs2 31..25=5 14..12=2 6..2=0x0E 1..0=3 -clmulhw rd rs1 rs2 31..25=5 14..12=3 6..2=0x0E 1..0=3 - shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 bextw rd rs1 rs2 31..25=4 14..12=6 6..2=0x0E 1..0=3 |