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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-03 18:09:58 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-03 18:09:58 -0800 |
| commit | c7e17632237219090791ba67dd700c2fca432e20 (patch) | |
| tree | f27522c5cb17b88ed7fd487f6e95dbefb8319fe9 /opcodes-rv32m | |
| parent | 5d52b6321b02840d2a64f1663900f15b7c9f22a2 (diff) | |
| download | riscv-opcodes-c7e17632237219090791ba67dd700c2fca432e20.zip riscv-opcodes-c7e17632237219090791ba67dd700c2fca432e20.tar.gz riscv-opcodes-c7e17632237219090791ba67dd700c2fca432e20.tar.bz2 | |
Factor out opcodes into per-extension files
Diffstat (limited to 'opcodes-rv32m')
| -rw-r--r-- | opcodes-rv32m | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes-rv32m b/opcodes-rv32m new file mode 100644 index 0000000..51e6786 --- /dev/null +++ b/opcodes-rv32m @@ -0,0 +1,8 @@ +mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 +mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 |