diff options
| author | Andrew Waterman <andrew@sifive.com> | 2021-03-08 14:38:23 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-08 14:38:23 -0800 |
| commit | ad36fb9f80a84154b6028592142988f0344054cc (patch) | |
| tree | 9897314712c251fd0a23a3e26f8e312cea14d60f /opcodes-rv32k | |
| parent | caf888b2141d4fd1eb46925f5de66bfdee524745 (diff) | |
| parent | f1e31a973d0eef1749bde2406986f12ea4501b5a (diff) | |
| download | riscv-opcodes-ad36fb9f80a84154b6028592142988f0344054cc.zip riscv-opcodes-ad36fb9f80a84154b6028592142988f0344054cc.tar.gz riscv-opcodes-ad36fb9f80a84154b6028592142988f0344054cc.tar.bz2 | |
Merge pull request #63 from ben-marshall/scalar-crypto
scalar-crypto: Add opcodes for RV32K, RV64K
Diffstat (limited to 'opcodes-rv32k')
| -rw-r--r-- | opcodes-rv32k | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/opcodes-rv32k b/opcodes-rv32k new file mode 100644 index 0000000..a9b2402 --- /dev/null +++ b/opcodes-rv32k @@ -0,0 +1,20 @@ + +# +# This file contains opcode specifications for the RISC-V +# Scalar Cryptographic instruction set extension. +# These instructions appear _only_ in RV32. +# ------------------------------------------------------------ + +# Scalar AES - RV32 +aes32esmi rt rs2 bs 11..7=0 29..25=0b11011 14..12=0 6..0=0x33 +aes32esi rt rs2 bs 11..7=0 29..25=0b11001 14..12=0 6..0=0x33 +aes32dsmi rt rs2 bs 11..7=0 29..25=0b11111 14..12=0 6..0=0x33 +aes32dsi rt rs2 bs 11..7=0 29..25=0b11101 14..12=0 6..0=0x33 + +# Scalar SHA512 - RV32 +sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 +sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 +sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 +sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 +sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 +sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 |