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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-14 23:19:39 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-31 10:07:27 -0700 |
| commit | 7231f5a8582019ca5eb0037ba05ceed8c44f35a8 (patch) | |
| tree | 973b77c507e337b43cfb71e056265de02c10b742 /opcodes-rv32h | |
| parent | 75f44b5b949922813b7ab971d5ececf863592b0a (diff) | |
| download | riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.zip riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.tar.gz riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.tar.bz2 | |
hyperviosr: add csr mask and interrupt macro name
This part copy the implementation which has been merged in spike
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'opcodes-rv32h')
| -rw-r--r-- | opcodes-rv32h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/opcodes-rv32h b/opcodes-rv32h new file mode 100644 index 0000000..84a361d --- /dev/null +++ b/opcodes-rv32h @@ -0,0 +1,14 @@ +# Hypervisor extension +hfence.vvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 +hfence.gvma 11..7=0 rs1 rs2 31..25=0x31 14..12=0 6..2=0x1C 1..0=3 + +hlv.b rd rs1 24..20=0x0 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.bu rd rs1 24..20=0x1 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.h rd rs1 24..20=0x0 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.hu rd rs1 24..20=0x1 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlvx.hu rd rs1 24..20=0x3 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.w rd rs1 24..20=0x0 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlvx.wu rd rs1 24..20=0x3 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hsv.b 11..7=0 rs1 rs2 31..25=0x31 14..12=4 6..2=0x1C 1..0=3 +hsv.h 11..7=0 rs1 rs2 31..25=0x33 14..12=4 6..2=0x1C 1..0=3 +hsv.w 11..7=0 rs1 rs2 31..25=0x35 14..12=4 6..2=0x1C 1..0=3 |