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| author | Andrew Waterman <andrew@sifive.com> | 2020-05-12 00:54:56 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-05-12 00:54:56 -0700 |
| commit | 8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275 (patch) | |
| tree | ed84df9d8a71eeef4117eb6c3ac8cc605853e610 /opcodes-rv32a | |
| parent | 36712402c3000db1b897cf2c021fb28f860262ad (diff) | |
| download | riscv-opcodes-8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275.zip riscv-opcodes-8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275.tar.gz riscv-opcodes-8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275.tar.bz2 | |
RVV v0.9: change vl1r/vs1r opcodes
https://github.com/riscv/riscv-v-spec/commit/5a0911c56394cc9ae2b5ade60a019cc82b2f926a
Diffstat (limited to 'opcodes-rv32a')
0 files changed, 0 insertions, 0 deletions