diff options
| author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2022-01-21 06:34:13 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-20 13:34:13 -0800 |
| commit | 9780234be4e34702f69d7bcce503f488cf14b327 (patch) | |
| tree | 580b0a22a6f15312a23fb706746f1392e52e7c4c /opcodes-rv32a | |
| parent | ba481c27b9ba9176851d3f03dde07a9e1db87aa8 (diff) | |
| download | riscv-opcodes-9780234be4e34702f69d7bcce503f488cf14b327.zip riscv-opcodes-9780234be4e34702f69d7bcce503f488cf14b327.tar.gz riscv-opcodes-9780234be4e34702f69d7bcce503f488cf14b327.tar.bz2 | |
Synchronize priv-instr-table.tex with the Manual (#99)
This commit roughly synchronizes privileged instruction table with the ISA
Manual with slight instruction order modifications, expecting instruction
tables in the ISA Manual are fully generated by riscv-opcodes,
not modified by hand.
This is based on:
* riscv/riscv-isa-manual: commit f30a5f6de685
("Update chapters 2 and 7 for Hypervisor v0.6")
* riscv/riscv-opcodes: commit 65af4131c26f
("Virtual memory updates (#76)")
Diffstat (limited to 'opcodes-rv32a')
0 files changed, 0 insertions, 0 deletions