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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-31 18:13:54 -0800 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-01-31 18:13:54 -0800 |
commit | 92b7ccecbf4ef36feaeaabc656fb0eb040fc7885 (patch) | |
tree | 8a2b1b0eacd47f35640e4a4a2a8f6c6343dd6886 /inst.v | |
parent | 4159b9b3fdbebf7f3000acec57257812663834d9 (diff) | |
download | riscv-opcodes-92b7ccecbf4ef36feaeaabc656fb0eb040fc7885.zip riscv-opcodes-92b7ccecbf4ef36feaeaabc656fb0eb040fc7885.tar.gz riscv-opcodes-92b7ccecbf4ef36feaeaabc656fb0eb040fc7885.tar.bz2 |
[opcodes] fixed verilog generation for shifts
Diffstat (limited to 'inst.v')
-rw-r--r-- | inst.v | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -12,12 +12,12 @@ `define BGEU 32'b?????_?????_?????_???????_111_1100011 `define LUI 32'b?????_????????????????????_0110111 `define ADDI 32'b?????_?????_????????????_000_0010011 -`define SLLI 32'b?????_?????_??????_000000_001_0010011 +`define SLLI 32'b?????_?????_000000_??????_001_0010011 `define SLTI 32'b?????_?????_????????????_010_0010011 `define SLTIU 32'b?????_?????_????????????_011_0010011 `define XORI 32'b?????_?????_????????????_100_0010011 -`define SRLI 32'b?????_?????_??????_000000_101_0010011 -`define SRAI 32'b?????_?????_??????_000000_101_0010011 +`define SRLI 32'b?????_?????_000000_??????_101_0010011 +`define SRAI 32'b?????_?????_000001_??????_101_0010011 `define ORI 32'b?????_?????_????????????_110_0010011 `define ANDI 32'b?????_?????_????????????_111_0010011 `define ADD 32'b?????_?????_?????_0000000000_0110011 @@ -39,9 +39,9 @@ `define REM 32'b?????_?????_?????_0000001110_0110011 `define REMU 32'b?????_?????_?????_0000001111_0110011 `define ADDIW 32'b?????_?????_????????????_000_0011011 -`define SLLIW 32'b?????_?????_0_?????_000000_001_0011011 -`define SRLIW 32'b?????_?????_0_?????_000000_101_0011011 -`define SRAIW 32'b?????_?????_0_?????_000000_101_0011011 +`define SLLIW 32'b?????_?????_000000_0_?????_001_0011011 +`define SRLIW 32'b?????_?????_000000_0_?????_101_0011011 +`define SRAIW 32'b?????_?????_000001_0_?????_101_0011011 `define ADDW 32'b?????_?????_?????_0000000000_0111011 `define SUBW 32'b?????_?????_?????_1000000000_0111011 `define SLLW 32'b?????_?????_?????_0000000001_0111011 |