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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-21 14:40:33 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-21 14:40:33 -0800 |
| commit | e9ad4cabe84d3f235278c8e2f920d9e776db21f7 (patch) | |
| tree | 6dc92aa845841d3744a31fd57b88e708034a3138 /inst.chisel | |
| parent | 2983e55547558ab4ca2865c9ecd517e077695730 (diff) | |
| download | riscv-opcodes-e9ad4cabe84d3f235278c8e2f920d9e776db21f7.zip riscv-opcodes-e9ad4cabe84d3f235278c8e2f920d9e776db21f7.tar.gz riscv-opcodes-e9ad4cabe84d3f235278c8e2f920d9e776db21f7.tar.bz2 | |
fix slli/slliw encoding bug
Diffstat (limited to 'inst.chisel')
| -rw-r--r-- | inst.chisel | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/inst.chisel b/inst.chisel index b77863a..abda1c6 100644 --- a/inst.chisel +++ b/inst.chisel @@ -10,7 +10,7 @@ def LUI = Bits("b?????????????????????????0110111") def AUIPC = Bits("b?????????????????????????0010111") def ADDI = Bits("b?????????????????000?????0010011") - def SLLI = Bits("b010000???????????001?????0010011") + def SLLI = Bits("b000000???????????001?????0010011") def SLTI = Bits("b?????????????????010?????0010011") def SLTIU = Bits("b?????????????????011?????0010011") def XORI = Bits("b?????????????????100?????0010011") @@ -37,7 +37,7 @@ def REM = Bits("b0000001??????????110?????0110011") def REMU = Bits("b0000001??????????111?????0110011") def ADDIW = Bits("b?????????????????000?????0011011") - def SLLIW = Bits("b0100000??????????001?????0011011") + def SLLIW = Bits("b0000000??????????001?????0011011") def SRLIW = Bits("b0000000??????????101?????0011011") def SRAIW = Bits("b0100000??????????101?????0011011") def ADDW = Bits("b0000000??????????000?????0111011") |