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| author | Tim Newsome <tim@sifive.com> | 2016-06-01 13:16:29 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2016-06-01 13:16:29 -0700 |
| commit | 1783043af1d4af65914f5ff2e167202abb7576c0 (patch) | |
| tree | e385aba35270f45a693126667123a33d218f3411 /encoding.h | |
| parent | c8bea5d3b61b04381221398f4085e34281a788b6 (diff) | |
| download | riscv-opcodes-1783043af1d4af65914f5ff2e167202abb7576c0.zip riscv-opcodes-1783043af1d4af65914f5ff2e167202abb7576c0.tar.gz riscv-opcodes-1783043af1d4af65914f5ff2e167202abb7576c0.tar.bz2 | |
Add dret instruction and debug CSRs. (#5)
Diffstat (limited to 'encoding.h')
| -rw-r--r-- | encoding.h | 23 |
1 files changed, 23 insertions, 0 deletions
@@ -33,6 +33,29 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 +#define DCSR_XDEBUGVER (3<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_HWBPCOUNT (0xfff<<16) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) |