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author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-06-27 14:33:19 +0900 |
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committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-06-27 14:48:12 +0900 |
commit | 42330be7eeeff35501c20652950f408a662dc3f7 (patch) | |
tree | 2e8b8bae9631cc681490d75fdfa99b6be43c9afd /constants.py | |
parent | 91ede9a7e3cafa3228028993df7a790c7bf55c55 (diff) | |
download | riscv-opcodes-42330be7eeeff35501c20652950f408a662dc3f7.zip riscv-opcodes-42330be7eeeff35501c20652950f408a662dc3f7.tar.gz riscv-opcodes-42330be7eeeff35501c20652950f408a662dc3f7.tar.bz2 |
Add 'Sstc' standard extension CSRs
cf. <https://github.com/riscv/riscv-time-compare/releases/tag/v0.5.4>
Diffstat (limited to 'constants.py')
-rw-r--r-- | constants.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/constants.py b/constants.py index 904ea38..5412751 100644 --- a/constants.py +++ b/constants.py @@ -112,6 +112,7 @@ csrs = [ (0x142, 'scause'), (0x143, 'stval'), (0x144, 'sip'), + (0x14D, 'stimecmp'), # Sstc (0x180, 'satp'), (0x5A8, 'scontext'), @@ -124,6 +125,7 @@ csrs = [ (0x242, 'vscause'), (0x243, 'vstval'), (0x244, 'vsip'), + (0x24D, 'vstimecmp'), # Sstc (0x280, 'vsatp'), (0x600, 'hstatus'), (0x602, 'hedeleg'), @@ -349,7 +351,11 @@ csrs = [ ] csrs32 = [ + # Standard Supervisor R/W + (0x15D, 'stimecmph'), # Sstc + # Standard Hypervisor R/w + (0x25D, 'vstimecmph'), # Sstc (0x615, 'htimedeltah'), (0x61A, 'henvcfgh'), (0x61C, 'hstateen0h'), # Smstateen |