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| author | Andrew Waterman <andrew@sifive.com> | 2024-05-01 01:38:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-05-01 01:46:31 -0700 |
| commit | 09879e6b56714aa705aa67705b1ccb215be427e5 (patch) | |
| tree | 9d881f0ba42e6d710a226c00b7879a1b2b8ab883 /constants.py | |
| parent | ba462efa5abc16469bc2c621f6b7c419a962f4b8 (diff) | |
| download | riscv-opcodes-09879e6b56714aa705aa67705b1ccb215be427e5.zip riscv-opcodes-09879e6b56714aa705aa67705b1ccb215be427e5.tar.gz riscv-opcodes-09879e6b56714aa705aa67705b1ccb215be427e5.tar.bz2 | |
Remove RV128 for now
It is highly speculative at this point, but it adds maintenance burden.
Diffstat (limited to 'constants.py')
| -rw-r--r-- | constants.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/constants.py b/constants.py index 3451ade..dc76ba3 100644 --- a/constants.py +++ b/constants.py @@ -157,11 +157,8 @@ emitted_pseudo_ops = [ 'rstsa16', 'rstsa32', 'srli32_u', - 'slli_rv128', 'slli_rv32', - 'srai_rv128', 'srai_rv32', - 'srli_rv128', 'srli_rv32', 'umax32', 'c_mop_1', |