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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-15 00:44:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-15 00:44:53 -0700 |
| commit | a52c518b8d2dc36051e1cbc61c519967deeaf60f (patch) | |
| tree | 729811def9421834f98e7c673c487fa4be3d94d9 /README.md | |
| parent | 8ecf5fd64d4df6e089f628e54538a809cd0c7b6e (diff) | |
| download | riscv-opcodes-a52c518b8d2dc36051e1cbc61c519967deeaf60f.zip riscv-opcodes-a52c518b8d2dc36051e1cbc61c519967deeaf60f.tar.gz riscv-opcodes-a52c518b8d2dc36051e1cbc61c519967deeaf60f.tar.bz2 | |
vext.x.v -> vmv.x.s
See https://github.com/riscv/riscv-v-spec/pull/247
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