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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 17:35:30 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 17:35:30 -0700 |
commit | 43ca48c7d1ff67af4286a93185fc83f75be4760f (patch) | |
tree | 23c9fedde6743be5b417f85a679d0e20162c45e2 /Makefile | |
parent | e37d3bd4d882776771ea27e4b1c5957b69950712 (diff) | |
download | riscv-opcodes-43ca48c7d1ff67af4286a93185fc83f75be4760f.zip riscv-opcodes-43ca48c7d1ff67af4286a93185fc83f75be4760f.tar.gz riscv-opcodes-43ca48c7d1ff67af4286a93185fc83f75be4760f.tar.bz2 |
Update to new privileged spec
Diffstat (limited to 'Makefile')
-rw-r--r-- | Makefile | 5 |
1 files changed, 3 insertions, 2 deletions
@@ -3,15 +3,16 @@ SHELL := /bin/sh ISASIM_H := ../riscv-isa-sim/riscv/encoding.h ISASIM_HWACHA_H := ../riscv-isa-sim/hwacha/opcodes_hwacha_ut.h PK_H := ../riscv-pk/pk/encoding.h +FESVR_H := ../riscv-fesvr/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h GAS_H := ../riscv-gnu-toolchain/binutils/include/opcode/riscv-opc.h XCC_H := ../riscv-gnu-toolchain/gcc/gcc/config/riscv/riscv-opc.h ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom -install: $(ISASIM_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex +install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex -$(ISASIM_H) $(PK_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes +$(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes cp encoding.h $@ cat opcodes | ./parse-opcodes -c >> $@ |