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authorQuan Nguyen <quannguyen@berkeley.edu>2014-01-20 15:48:52 -0800
committerQuan Nguyen <quannguyen@berkeley.edu>2014-01-20 15:48:52 -0800
commit714662af27924f1c3dbf81d700e67dfafa0367a0 (patch)
tree0b4842f87b1cbfe7788d02a74e168005b78cb31d /Makefile
parentd372a0e5a897f499178c38851e17c3bd82e672c1 (diff)
parent612076a5c7b8e3e5625e5a0d803d6faa2f402737 (diff)
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Merge branch 'confprec'
Conflicts: Makefile
Diffstat (limited to 'Makefile')
-rw-r--r--Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index 20d430f..4bc2d18 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,7 @@ ENV_H := ../riscv-tests/env/encoding.h
GAS_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h
XCC_H := ../riscv-gcc/gcc-4.6.1/gcc/config/riscv/riscv-opc.h
-ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-custom
+ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom
install: $(ISASIM_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex