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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2012-03-03 15:12:44 -0800 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2012-03-03 15:12:44 -0800 |
commit | d5cb229de8bcacf13ce7bf07736b2e756bebb690 (patch) | |
tree | 4c6ccc5f3f83e6d620936536423951bb08f3a70c /Makefile | |
parent | 8b7d325b53667ff123531325a410f40e5dd0373a (diff) | |
download | riscv-opcodes-d5cb229de8bcacf13ce7bf07736b2e756bebb690.zip riscv-opcodes-d5cb229de8bcacf13ce7bf07736b2e756bebb690.tar.gz riscv-opcodes-d5cb229de8bcacf13ce7bf07736b2e756bebb690.tar.bz2 |
new instructions to handle vector exceptions
Diffstat (limited to 'Makefile')
-rwxr-xr-x | Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -1,6 +1,6 @@ -ISASIM_H := ../riscv-isa-run/riscv/opcodes.h +ISASIM_H := ../riscv-isa-sim/riscv/opcodes.h PK_H := ../riscv-pk/pk/riscv-opc.h -XCC_H := ../riscv-gcc/src/include/opcode/mips-riscv-opc.h +XCC_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h install: $(ISASIM_H) $(PK_H) $(XCC_H) inst.v instr-table.tex |