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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-13 20:09:28 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 18:23:12 -0700 |
| commit | 73b3d3e819c341d76240365bc7c892fc686795fb (patch) | |
| tree | 4b7b070ce986fbc8911b5d49e44be79f02e934d9 /Makefile | |
| parent | d8ea6f0401621201503c6f9b259a2ac4cf7b19aa (diff) | |
| download | riscv-opcodes-73b3d3e819c341d76240365bc7c892fc686795fb.zip riscv-opcodes-73b3d3e819c341d76240365bc7c892fc686795fb.tar.gz riscv-opcodes-73b3d3e819c341d76240365bc7c892fc686795fb.tar.bz2 | |
rvv: add vector register field and control register
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions