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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-07-19 19:15:58 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-19 16:15:58 -0700 |
| commit | 65af4131c26fb4743fee4c4efbdff8a59eb4e48a (patch) | |
| tree | 2a74f0d7e94ae3af3a63f2d3d0d5cd466af49385 /Makefile | |
| parent | e46f324eec2f783803fa776f589b9ef047db3af7 (diff) | |
| download | riscv-opcodes-65af4131c26fb4743fee4c4efbdff8a59eb4e48a.zip riscv-opcodes-65af4131c26fb4743fee4c4efbdff8a59eb4e48a.tar.gz riscv-opcodes-65af4131c26fb4743fee4c4efbdff8a59eb4e48a.tar.bz2 | |
Virtual memory updates (#76)
* Add Svinval instructions
* Add PTE defines for Priv 1.12 and Svpbmt
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -5,7 +5,7 @@ PK_H := ../riscv-pk/machine/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k +ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo |