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| author | Ben Marshall <ben.marshall@bristol.ac.uk> | 2021-07-23 12:58:02 +0100 |
|---|---|---|
| committer | Ben Marshall <ben.marshall@bristol.ac.uk> | 2021-07-23 12:58:02 +0100 |
| commit | fa77a73ce263f2e471730ee086000153bb3efa25 (patch) | |
| tree | a65cadc4e5e4e64f816024561dc31c61f71f9952 | |
| parent | 65af4131c26fb4743fee4c4efbdff8a59eb4e48a (diff) | |
| download | riscv-opcodes-fa77a73ce263f2e471730ee086000153bb3efa25.zip riscv-opcodes-fa77a73ce263f2e471730ee086000153bb3efa25.tar.gz riscv-opcodes-fa77a73ce263f2e471730ee086000153bb3efa25.tar.bz2 | |
scalar-crypto: post arch-review aes32* opcode change
- After questions from the architecture review and subsequent cryptography
task group meetings, we have stopped overlapping the aes32* and aes64*
instruction encodings.
- We've done this in the name of removing complexity, because opcode space is
not as tight as we thought it was when we originally overlapped them.
- Change affected by updating the aes32* opcodes only.
On branch master
Your branch is up-to-date with 'origin/master'.
Changes to be committed:
modified: opcodes-rv32k
modified: parse_opcodes
| -rw-r--r-- | opcodes-rv32k | 8 | ||||
| -rwxr-xr-x | parse_opcodes | 8 |
2 files changed, 4 insertions, 12 deletions
diff --git a/opcodes-rv32k b/opcodes-rv32k index fb4c876..56ed607 100644 --- a/opcodes-rv32k +++ b/opcodes-rv32k @@ -6,10 +6,10 @@ # ------------------------------------------------------------ # Scalar AES - RV32 -aes32esmi rd rs1 rs2 bs 29..25=0b11011 14..12=0 6..0=0x33 -aes32esi rd rs1 rs2 bs 29..25=0b11001 14..12=0 6..0=0x33 -aes32dsmi rd rs1 rs2 bs 29..25=0b11111 14..12=0 6..0=0x33 -aes32dsi rd rs1 rs2 bs 29..25=0b11101 14..12=0 6..0=0x33 +aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 +aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 +aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 +aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 # Scalar SHA512 - RV32 sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 diff --git a/parse_opcodes b/parse_opcodes index 7bb4dc9..603ae05 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -58,10 +58,6 @@ arglut['zimm11'] = (30,20) # Instructions which are _only_ in RV32 rv32_only = [ - "aes32esmi", - "aes32esi", - "aes32dsmi", - "aes32dsi", "sha512sum0r", "sha512sum1r", "sha512sig0l", @@ -75,10 +71,6 @@ rv64_only = [ "aes64ks1i", "aes64im", "aes64ks2", - "aes64esm", - "aes64es", - "aes64dsm", - "aes64ds", "sha512sum0", "sha512sum1", "sha512sig0", |