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| author | Tsukasa #01 (a4lg) <research_trasio@irq.a4lg.com> | 2022-01-20 11:33:58 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-19 18:33:58 -0800 |
| commit | f2f4583551fedeb2b9eb5423f7dd6a7f1ada0696 (patch) | |
| tree | e3a15cda64ebc067992de2f8cf66fe550161041a | |
| parent | f55eece0b9e5526628f7180eb6d1580ad73bd5d0 (diff) | |
| download | riscv-opcodes-f2f4583551fedeb2b9eb5423f7dd6a7f1ada0696.zip riscv-opcodes-f2f4583551fedeb2b9eb5423f7dd6a7f1ada0696.tar.gz riscv-opcodes-f2f4583551fedeb2b9eb5423f7dd6a7f1ada0696.tar.bz2 | |
Add RISC-V Zfh extension instructions to table (#97)
| -rwxr-xr-x | parse_opcodes | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/parse_opcodes b/parse_opcodes index 2d83501..a29180f 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -1005,6 +1005,23 @@ def make_latex_table(): print_subtitle('RV64Q Standard Extension (in addition to RV32Q)') print_insts('fcvt.l.q', 'fcvt.lu.q') print_insts('fcvt.q.l', 'fcvt.q.lu') + print_footer() + + print_header('r','r4','i','s') + print_subtitle('RV32Zfh Standard Extension') + print_insts('flh', 'fsh') + print_insts('fmadd.h', 'fmsub.h', 'fnmsub.h', 'fnmadd.h') + print_insts('fadd.h', 'fsub.h', 'fmul.h', 'fdiv.h', 'fsqrt.h') + print_insts('fsgnj.h', 'fsgnjn.h', 'fsgnjx.h', 'fmin.h', 'fmax.h') + print_insts('fcvt.s.h', 'fcvt.h.s') + print_insts('fcvt.d.h', 'fcvt.h.d') + print_insts('fcvt.q.h', 'fcvt.h.q') + print_insts('feq.h', 'flt.h', 'fle.h', 'fclass.h') + print_insts('fcvt.w.h', 'fcvt.wu.h', 'fmv.x.h') + print_insts('fcvt.h.w', 'fcvt.h.wu', 'fmv.h.x') + print_subtitle('RV64Zfh Standard Extension (in addition to RV32Zfh)') + print_insts('fcvt.l.h', 'fcvt.lu.h') + print_insts('fcvt.h.l', 'fcvt.h.lu') print_footer('\\caption{Instruction listing for RISC-V}') def print_chisel_insn(name): |