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| author | Neel Gala <neelgala@incoresemi.com> | 2022-04-11 11:30:45 +0530 |
|---|---|---|
| committer | Neel Gala <neelgala@incoresemi.com> | 2022-04-11 11:30:45 +0530 |
| commit | bcf0a019a5ab6c467acd39147ced59ca0d0b4852 (patch) | |
| tree | cda150f7c91ee9176dcf3f7ae8610078bc3563ee | |
| parent | 1ad98bac0c4e0264b962e95f4b52a2591ba8ec74 (diff) | |
| download | riscv-opcodes-bcf0a019a5ab6c467acd39147ced59ca0d0b4852.zip riscv-opcodes-bcf0a019a5ab6c467acd39147ced59ca0d0b4852.tar.gz riscv-opcodes-bcf0a019a5ab6c467acd39147ced59ca0d0b4852.tar.bz2 | |
migrate V-extension aliases
| -rw-r--r-- | opcodes-rvv-pseudo | 18 | ||||
| -rw-r--r-- | rv_v_aliases | 18 |
2 files changed, 18 insertions, 18 deletions
diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo deleted file mode 100644 index 35cf095..0000000 --- a/opcodes-rvv-pseudo +++ /dev/null @@ -1,18 +0,0 @@ -# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v -@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 - -@vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -@vl2r.v 31..26=1 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -@vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -@vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 - -@vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 -@vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 - -@vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -@vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -@vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 - -@vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -@vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 diff --git a/rv_v_aliases b/rv_v_aliases new file mode 100644 index 0000000..0f7aaa6 --- /dev/null +++ b/rv_v_aliases @@ -0,0 +1,18 @@ +# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v +#@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 + +$pseudo_op rv_v::vl1re8.v vl1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl2re8.v vl2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl4re8.v vl4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl8re8.v vl8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 + +$pseudo_op rv_v::vlm.v vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vsm.v vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 + +$pseudo_op rv_v::vfredusum.vs vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +$pseudo_op rv_v::vfwredusum.vs vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +$pseudo_op rv_v::vcpop.m vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 + +$pseudo_op rv_v::vmorn.mm vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +$pseudo_op rv_v::vmandn.mm vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 |