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author | Afonso Oliveira <Afonso.Oliveira@synopsys.com> | 2024-08-28 10:57:12 +0100 |
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committer | Afonso Oliveira <Afonso.Oliveira@synopsys.com> | 2024-08-28 10:57:12 +0100 |
commit | 69258f2661ef972ff3fc0d8903f222690158f271 (patch) | |
tree | 2290df1264769de4c15cb3a08f4e2c9e73d8b8d9 | |
parent | 07b95c53a2585412f1a9044716445eb87af1e9d5 (diff) | |
download | riscv-opcodes-69258f2661ef972ff3fc0d8903f222690158f271.zip riscv-opcodes-69258f2661ef972ff3fc0d8903f222690158f271.tar.gz riscv-opcodes-69258f2661ef972ff3fc0d8903f222690158f271.tar.bz2 |
Added Pseudo-instructions from F and D. Allow for instructions to have a special field
Signed-off-by: Afonso Oliveira <Afonso.Oliveira@synopsys.com>
-rwxr-xr-x | parse.py | 29 | ||||
-rw-r--r-- | rv_d | 6 | ||||
-rw-r--r-- | rv_f | 5 |
3 files changed, 31 insertions, 9 deletions
@@ -113,16 +113,27 @@ def process_enc_line(line, ext): encoding_args = encoding.copy() for a in args: if a not in arg_lut: - logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') - raise SystemExit(1) - else: - (msb, lsb) = arg_lut[a] - for ind in range(lsb, msb + 1): - # overlapping bits - if encoding_args[31 - ind] != '-': - logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[31 - ind]} variable in bit {ind}') + if len(parts := a.split('=')) == 2: + existing_arg, new_arg = parts + if existing_arg in arg_lut: + print ("old",arg_lut) + arg_lut[a] = arg_lut[existing_arg] + print ("new\n", arg_lut) + + else: + logging.error(f' Found field {existing_arg} in variable {a} in instruction {name} whose mapping in arg_lut does not exist') raise SystemExit(1) - encoding_args[31 - ind] = a + else: + logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') + raise SystemExit(1) + (msb, lsb) = arg_lut[a] + for ind in range(lsb, msb + 1): + # overlapping bits + if encoding_args[31 - ind] != '-': + logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[31 - ind]} variable in bit {ind}') + raise SystemExit(1) + encoding_args[31 - ind] = a + # update the fields of the instruction as a dict and return back along with # the name of the instruction @@ -24,3 +24,9 @@ fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 + +#pseudoinstructions +$pseudo_op rv_d::fsgnj.d fmv.d rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 +$pseudo_op rv_d::fsgnjx.d fabs.d rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 +$pseudo_op rv_d::fsgnjn.d fneg.d rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 +
\ No newline at end of file @@ -29,6 +29,11 @@ fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 +#pseudointructions +$pseudo_op rv_f::fsgnj.s fmv.s rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fsgnjx.s fabs.s rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fsgnjn.s fneg.s rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 + #CSRs $pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 $pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 |