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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-22 16:03:59 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-22 16:03:59 -0500 |
| commit | 41c6b4dd2177554e6476ad51f9d0cff8423bf356 (patch) | |
| tree | 2e144ad27ae0745f490815ae77a5e9f5ce575f12 | |
| parent | 7206bf6c551fb32aa8c7f94c39da88f447f1ca20 (diff) | |
| parent | 14c5be068c9928a7a43f507716dd3550f9e325ca (diff) | |
| download | riscv-opcodes-41c6b4dd2177554e6476ad51f9d0cff8423bf356.zip riscv-opcodes-41c6b4dd2177554e6476ad51f9d0cff8423bf356.tar.gz riscv-opcodes-41c6b4dd2177554e6476ad51f9d0cff8423bf356.tar.bz2 | |
Merge pull request #276 from foss-for-synopsys-dwc-arc-processors/UpdateDB
Move F extension CSRs to the rv_f
| -rw-r--r-- | rv_f | 9 | ||||
| -rw-r--r-- | rv_zicsr | 11 |
2 files changed, 9 insertions, 11 deletions
@@ -29,3 +29,12 @@ fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 +#CSRs +$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 @@ -4,14 +4,3 @@ csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 - -$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 - - |