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| author | Zhen Wei <zhen.wei@sifive.com> | 2021-07-13 17:50:10 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-13 02:50:10 -0700 |
| commit | 418452b145279d3ace30c7052c66109c931f8b19 (patch) | |
| tree | 3d40c438c8b0dad7701ba89419d41cc85b4923ec | |
| parent | cab0dc75afb09fdf0410aa4d1c5a14088d767cba (diff) | |
| download | riscv-opcodes-418452b145279d3ace30c7052c66109c931f8b19.zip riscv-opcodes-418452b145279d3ace30c7052c66109c931f8b19.tar.gz riscv-opcodes-418452b145279d3ace30c7052c66109c931f8b19.tar.bz2 | |
Updated several RVV instructions (#74)
| -rw-r--r-- | opcodes-rvv | 25 | ||||
| -rw-r--r-- | opcodes-rvv-pseudo | 5 |
2 files changed, 20 insertions, 10 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index f2ac1c4..7b2d7ec 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -18,8 +18,8 @@ vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 # # Vector Unit-Stride Instructions (including segment part) # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions -vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 -vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 +vlm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +vsm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 @@ -176,7 +176,7 @@ vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # OPFVV vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 @@ -234,7 +234,7 @@ vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredusum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 @@ -262,9 +262,11 @@ vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmadc.vxm 31..26=0x11 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vxm 31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vx 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsbc.vxm 31..26=0x13 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vxm 31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vx 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 @@ -305,9 +307,11 @@ vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmadc.vvm 31..26=0x11 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vvm 31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vv 31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsbc.vvm 31..26=0x13 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vvm 31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vv 31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 @@ -352,7 +356,8 @@ vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmadc.vim 31..26=0x11 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vi 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 @@ -418,7 +423,7 @@ vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 -vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 +vcpop.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo index 6cf2bf4..1530ad8 100644 --- a/opcodes-rvv-pseudo +++ b/opcodes-rvv-pseudo @@ -5,3 +5,8 @@ @vl2r.v 31..26=1 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 @vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 @vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 + +@vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +@vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +@vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 |