diff options
| author | Andrew Waterman <andrew@sifive.com> | 2020-07-21 16:41:10 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-07-21 16:41:10 -0700 |
| commit | 0688bb090a426a34c4ee7a0b5d0b6fff67e1b0ea (patch) | |
| tree | 6a3795d257b651dada74e8809604b784fbf54e3c | |
| parent | de0aeefcc4c9cf0806b29e03822e2978556feb04 (diff) | |
| download | riscv-opcodes-0688bb090a426a34c4ee7a0b5d0b6fff67e1b0ea.zip riscv-opcodes-0688bb090a426a34c4ee7a0b5d0b6fff67e1b0ea.tar.gz riscv-opcodes-0688bb090a426a34c4ee7a0b5d0b6fff67e1b0ea.tar.bz2 | |
Incorporate whole-register load/store changes in RVV v1.0-draft
https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5
| -rw-r--r-- | opcodes-rvv | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 2633e89..cd7aaba 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -62,8 +62,26 @@ vle64ff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 # Vector Load/Store Whole Registers # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions -vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vs1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 # Vector Floating-Point Instructions # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions |