Merge remote-tracking branch 'origin/priv-1.10'

5 files changed, 87 insertions, 48 deletions

diff --git a/Makefile b/Makefile
index 3220e47..795cb94 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@ GAS_H := ../riscv-gnu-toolchain/riscv-binutils-gdb/include/opcode/riscv-opc.h
 
 ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom
 
-install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) inst.chisel instr-table.tex priv-instr-table.tex
+install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) inst.chisel instr-table.tex priv-instr-table.tex
 
 $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes encoding.h
 	cp encoding.h $@
diff --git a/encoding.h b/encoding.h
index 85e97be..97ddbec 100644
--- a/encoding.h
+++ b/encoding.h
@@ -17,10 +17,14 @@
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
 #define MSTATUS_MPRV        0x00020000
-#define MSTATUS_PUM         0x00040000
+#define MSTATUS_SUM         0x00040000
 #define MSTATUS_MXR         0x00080000
-#define MSTATUS_VM          0x1F000000
+#define MSTATUS_TVM         0x00100000
+#define MSTATUS_TW          0x00200000
+#define MSTATUS_TSR         0x00400000
 #define MSTATUS32_SD        0x80000000
+#define MSTATUS_UXL         0x0000000300000000
+#define MSTATUS_SXL         0x0000000C00000000
 #define MSTATUS64_SD        0x8000000000000000
 
 #define SSTATUS_UIE         0x00000001
@@ -30,8 +34,10 @@
 #define SSTATUS_SPP         0x00000100
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
-#define SSTATUS_PUM         0x00040000
+#define SSTATUS_SUM         0x00040000
+#define SSTATUS_MXR         0x00080000
 #define SSTATUS32_SD        0x80000000
+#define SSTATUS_UXL         0x0000000300000000
 #define SSTATUS64_SD        0x8000000000000000
 
 #define DCSR_XDEBUGVER      (3U<<30)
@@ -107,12 +113,30 @@
 #define PRV_H 2
 #define PRV_M 3
 
-#define VM_MBARE 0
-#define VM_MBB   1
-#define VM_MBBID 2
-#define VM_SV32  8
-#define VM_SV39  9
-#define VM_SV48  10
+#define SPTBR32_MODE 0x80000000
+#define SPTBR32_ASID 0x7FC00000
+#define SPTBR32_PPN  0x003FFFFF
+#define SPTBR64_MODE 0xF000000000000000
+#define SPTBR64_ASID 0x0FFFF00000000000
+#define SPTBR64_PPN  0x00000FFFFFFFFFFF
+
+#define SPTBR_MODE_OFF  0
+#define SPTBR_MODE_SV32 1
+#define SPTBR_MODE_SV39 8
+#define SPTBR_MODE_SV48 9
+#define SPTBR_MODE_SV57 10
+#define SPTBR_MODE_SV64 11
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
 
 #define IRQ_S_SOFT   1
 #define IRQ_H_SOFT   2
@@ -127,9 +151,8 @@
 #define IRQ_HOST     13
 
 #define DEFAULT_RSTVEC     0x00001000
-#define DEFAULT_NMIVEC     0x00001004
-#define DEFAULT_MTVEC      0x00001010
-#define CONFIG_STRING_ADDR 0x0000100C
+#define CLINT_BASE         0x02000000
+#define CLINT_SIZE         0x000c0000
 #define EXT_IO_BASE        0x40000000
 #define DRAM_BASE          0x80000000
 
@@ -154,10 +177,12 @@
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
 # define RISCV_PGLEVEL_BITS 9
+# define SPTBR_MODE SPTBR64_MODE
 #else
 # define MSTATUS_SD MSTATUS32_SD
 # define SSTATUS_SD SSTATUS32_SD
 # define RISCV_PGLEVEL_BITS 10
+# define SPTBR_MODE SPTBR32_MODE
 #endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
@@ -171,30 +196,18 @@
   __tmp; })
 
 #define write_csr(reg, val) ({ \
-  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-    asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
-  else \
-    asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
 
 #define swap_csr(reg, val) ({ unsigned long __tmp; \
-  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
-    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
-  else \
-    asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
   __tmp; })
 
 #define set_csr(reg, bit) ({ unsigned long __tmp; \
-  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
-  else \
-    asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
   __tmp; })
 
 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
-  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
-    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
-  else \
-    asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
   __tmp; })
 
 #define rdtime() read_csr(time)
diff --git a/opcodes b/opcodes
index e4cc6a6..4303abd 100644
--- a/opcodes
+++ b/opcodes
@@ -117,10 +117,9 @@ ecall     11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
 ebreak    11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
 uret      11..7=0 19..15=0 31..20=0x002 14..12=0 6..2=0x1C 1..0=3
 sret      11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3
-hret      11..7=0 19..15=0 31..20=0x202 14..12=0 6..2=0x1C 1..0=3
 mret      11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3
 dret      11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3
-sfence.vm 11..7=0 rs1      31..20=0x104 14..12=0 6..2=0x1C 1..0=3
+sfence.vma 11..7=0 rs1 rs2 31..25=0x09  14..12=0 6..2=0x1C 1..0=3
 wfi       11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3
 csrrw     rd      rs1      imm12        14..12=1 6..2=0x1C 1..0=3
 csrrs     rd      rs1      imm12        14..12=2 6..2=0x1C 1..0=3
@@ -185,7 +184,7 @@ fcvt.w.s  rd rs1 24..20=0 31..27=0x18 rm       26..25=0 6..2=0x14 1..0=3
 fcvt.wu.s rd rs1 24..20=1 31..27=0x18 rm       26..25=0 6..2=0x14 1..0=3
 fcvt.l.s  rd rs1 24..20=2 31..27=0x18 rm       26..25=0 6..2=0x14 1..0=3
 fcvt.lu.s rd rs1 24..20=3 31..27=0x18 rm       26..25=0 6..2=0x14 1..0=3
-fmv.x.s   rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3
+fmv.x.w   rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3
 fclass.s  rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3
 
 fcvt.w.d  rd rs1 24..20=0 31..27=0x18 rm       26..25=1 6..2=0x14 1..0=3
@@ -206,7 +205,7 @@ fcvt.s.w  rd rs1 24..20=0 31..27=0x1A rm       26..25=0 6..2=0x14 1..0=3
 fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm       26..25=0 6..2=0x14 1..0=3
 fcvt.s.l  rd rs1 24..20=2 31..27=0x1A rm       26..25=0 6..2=0x14 1..0=3
 fcvt.s.lu rd rs1 24..20=3 31..27=0x1A rm       26..25=0 6..2=0x14 1..0=3
-fmv.s.x   rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
+fmv.w.x   rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
 
 fcvt.d.w  rd rs1 24..20=0 31..27=0x1A rm       26..25=1 6..2=0x14 1..0=3
 fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm       26..25=1 6..2=0x14 1..0=3
diff --git a/opcodes-pseudo b/opcodes-pseudo
index effae54..ab713f5 100644
--- a/opcodes-pseudo
+++ b/opcodes-pseudo
@@ -22,3 +22,7 @@
 # Old names for ecall/ebreak
 @scall     11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
 @sbreak    11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
+
+# Old names for fmv.x.w/fmv.w.x
+@fmv.x.s   rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3
+@fmv.s.x   rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 2a5de5b..408ed0c 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -33,17 +33,20 @@ arglut['vseglen'] = (31,29)
 
 causes = [
   (0x00, 'misaligned fetch'),
-  (0x01, 'fault fetch'),
+  (0x01, 'fetch access'),
   (0x02, 'illegal instruction'),
   (0x03, 'breakpoint'),
   (0x04, 'misaligned load'),
-  (0x05, 'fault load'),
+  (0x05, 'load access'),
   (0x06, 'misaligned store'),
-  (0x07, 'fault store'),
+  (0x07, 'store access'),
   (0x08, 'user_ecall'),
   (0x09, 'supervisor_ecall'),
   (0x0A, 'hypervisor_ecall'),
   (0x0B, 'machine_ecall'),
+  (0x0C, 'fetch page fault'),
+  (0x0D, 'load page fault'),
+  (0x0F, 'store page fault'),
 ]
 
 csrs = [
@@ -90,6 +93,7 @@ csrs = [
   (0x100, 'sstatus'),
   (0x104, 'sie'),
   (0x105, 'stvec'),
+  (0x106, 'scounteren'),
   (0x140, 'sscratch'),
   (0x141, 'sepc'),
   (0x142, 'scause'),
@@ -104,11 +108,32 @@ csrs = [
   (0x303, 'mideleg'),
   (0x304, 'mie'),
   (0x305, 'mtvec'),
+  (0x306, 'mcounteren'),
   (0x340, 'mscratch'),
   (0x341, 'mepc'),
   (0x342, 'mcause'),
   (0x343, 'mbadaddr'),
   (0x344, 'mip'),
+  (0x3a0, 'pmpcfg0'),
+  (0x3a1, 'pmpcfg1'),
+  (0x3a2, 'pmpcfg2'),
+  (0x3a3, 'pmpcfg3'),
+  (0x3b0, 'pmpaddr0'),
+  (0x3b1, 'pmpaddr1'),
+  (0x3b2, 'pmpaddr2'),
+  (0x3b3, 'pmpaddr3'),
+  (0x3b4, 'pmpaddr4'),
+  (0x3b5, 'pmpaddr5'),
+  (0x3b6, 'pmpaddr6'),
+  (0x3b7, 'pmpaddr7'),
+  (0x3b8, 'pmpaddr8'),
+  (0x3b9, 'pmpaddr9'),
+  (0x3ba, 'pmpaddr10'),
+  (0x3bb, 'pmpaddr11'),
+  (0x3bc, 'pmpaddr12'),
+  (0x3bd, 'pmpaddr13'),
+  (0x3be, 'pmpaddr14'),
+  (0x3bf, 'pmpaddr15'),
   (0x7a0, 'tselect'),
   (0x7a1, 'tdata1'),
   (0x7a2, 'tdata2'),
@@ -147,8 +172,6 @@ csrs = [
   (0xB1D, 'mhpmcounter29'),
   (0xB1E, 'mhpmcounter30'),
   (0xB1F, 'mhpmcounter31'),
-  (0x320, 'mucounteren'),
-  (0x321, 'mscounteren'),
   (0x323, 'mhpmevent3'),
   (0x324, 'mhpmevent4'),
   (0x325, 'mhpmevent5'),
@@ -635,7 +658,7 @@ def print_header(*types):
 \\multicolumn{1}{c|}{rs1} &
 \\multicolumn{1}{c|}{funct3} &
 \\multicolumn{1}{c|}{imm[4:1$\\vert$11]} &
-\\multicolumn{1}{c|}{opcode} & SB-type \\\\
+\\multicolumn{1}{c|}{opcode} & B-type \\\\
 \\cline{2-11}
 """
   if 'u' in types:
@@ -651,7 +674,7 @@ def print_header(*types):
 &
 \\multicolumn{8}{|c|}{imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]} &
 \\multicolumn{1}{c|}{rd} &
-\\multicolumn{1}{c|}{opcode} & UJ-type \\\\
+\\multicolumn{1}{c|}{opcode} & J-type \\\\
 \\cline{2-11}
 """
 
@@ -675,8 +698,6 @@ def print_footer(caption=''):
   """ % caption
 
 def print_inst(n):
-  is_system = (match[n] & 0x7f) == (match['scall'] & 0x7f)
-
   if n == 'fence' or n == 'fence.i':
     print_fence_type(n, match[n], arguments[n])
   elif 'aqrl' in arguments[n]:
@@ -689,9 +710,9 @@ def print_inst(n):
     print_u_type(n, match[n], arguments[n])
   elif 'jimm20' in arguments[n]:
     print_uj_type(n, match[n], arguments[n])
-  elif is_system and n[:3] == 'csr':
+  elif n[:3] == 'csr':
     print_csr_type(n, match[n], arguments[n])
-  elif 'imm12' in arguments[n] or is_system:
+  elif 'imm12' in arguments[n] or n == 'ecall' or n == 'ebreak':
     print_i_type(n, match[n], arguments[n])
   elif 'imm12hi' in arguments[n]:
     print_s_type(n, match[n], arguments[n])
@@ -708,12 +729,14 @@ def print_insts(*names):
 
 def make_supervisor_latex_table():
   print_header('i')
+  print_subtitle('Environment Call and Breakpoint')
+  print_insts('ecall', 'ebreak')
   print_subtitle('Trap-Return Instructions')
-  print_insts('uret', 'sret', 'hret', 'mret')
+  print_insts('uret', 'sret', 'mret')
   print_subtitle('Interrupt-Management Instructions')
   print_insts('wfi')
   print_subtitle('Memory-Management Instructions')
-  print_insts('sfence.vm')
+  print_insts('sfence.vma')
   print_footer('\\caption{RISC-V Privileged Instructions}')
 
 def make_latex_table():
@@ -759,9 +782,9 @@ def make_latex_table():
   print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s')
   print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s')
   print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s', 'fmin.s', 'fmax.s')
-  print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s')
+  print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.w')
   print_insts('feq.s', 'flt.s', 'fle.s', 'fclass.s')
-  print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x')
+  print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.w.x')
   print_footer()
 
   print_header('r','r4','i','s')