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authorAndrew Waterman <andrew@sifive.com>2017-03-27 14:25:34 -0700
committerAndrew Waterman <andrew@sifive.com>2017-03-27 14:25:34 -0700
commitd86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd (patch)
tree323490f997d9daabaf7d1d1333ee85b50405d8bb
parent771cd8afc10b438c1e7e8109287d40cb6bd3eddb (diff)
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Separate page faults from physical memory access exceptions
-rw-r--r--encoding.h5
-rwxr-xr-xparse-opcodes9
2 files changed, 8 insertions, 6 deletions
diff --git a/encoding.h b/encoding.h
index 99a75ea..e6478b2 100644
--- a/encoding.h
+++ b/encoding.h
@@ -147,9 +147,8 @@
#define IRQ_HOST 13
#define DEFAULT_RSTVEC 0x00001000
-#define DEFAULT_NMIVEC 0x00001004
-#define DEFAULT_MTVEC 0x00001010
-#define CONFIG_STRING_ADDR 0x0000100C
+#define CLINT_BASE 0x02000000
+#define CLINT_SIZE 0x000c0000
#define EXT_IO_BASE 0x40000000
#define DRAM_BASE 0x80000000
diff --git a/parse-opcodes b/parse-opcodes
index 0b375b3..58ebcef 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -33,17 +33,20 @@ arglut['vseglen'] = (31,29)
causes = [
(0x00, 'misaligned fetch'),
- (0x01, 'fault fetch'),
+ (0x01, 'fetch access'),
(0x02, 'illegal instruction'),
(0x03, 'breakpoint'),
(0x04, 'misaligned load'),
- (0x05, 'fault load'),
+ (0x05, 'load access'),
(0x06, 'misaligned store'),
- (0x07, 'fault store'),
+ (0x07, 'store access'),
(0x08, 'user_ecall'),
(0x09, 'supervisor_ecall'),
(0x0A, 'hypervisor_ecall'),
(0x0B, 'machine_ecall'),
+ (0x0C, 'fetch page fault'),
+ (0x0D, 'load page fault'),
+ (0x0F, 'store page fault'),
]
csrs = [