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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-08 14:33:12 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-08 14:33:12 -0800 |
| commit | cd10c7174835240b86a8ca72ce17aa7422d4970f (patch) | |
| tree | 7ee2b5a9a74983910fa789cc35937397b84d29fc | |
| parent | 3c1a9110b71658f6e3249186e8b44e7474a4ee90 (diff) | |
| download | riscv-opcodes-cd10c7174835240b86a8ca72ce17aa7422d4970f.zip riscv-opcodes-cd10c7174835240b86a8ca72ce17aa7422d4970f.tar.gz riscv-opcodes-cd10c7174835240b86a8ca72ce17aa7422d4970f.tar.bz2 | |
Encode VM type in sptbr, not mstatus
https://github.com/riscv/riscv-isa-manual/issues/4
| -rw-r--r-- | encoding.h | 14 |
1 files changed, 14 insertions, 0 deletions
@@ -114,6 +114,20 @@ #define VM_SV39 9 #define VM_SV48 10 +#define SPTBR32_MODE 0x80000000 +#define SPTBR32_ASID 0x7FC00000 +#define SPTBR32_PPN 0x003FFFFF +#define SPTBR64_MODE 0xE000000000000000 +#define SPTBR64_ASID 0x1FFFE00000000000 +#define SPTBR64_PPN 0x0000003FFFFFFFFF + +#define SPTBR_MODE_OFF 0 +#define SPTBR_MODE_SV32 1 +#define SPTBR_MODE_SV39 4 +#define SPTBR_MODE_SV48 5 +#define SPTBR_MODE_SV57 6 +#define SPTBR_MODE_SV64 7 + #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 |