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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:40:29 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:40:29 -0800 |
| commit | b6747a260e225c3eacc354335e7f12ff4b7b1f3e (patch) | |
| tree | d282d648c023be190fad29ef5a12965ba64563d6 | |
| parent | 282321b3a43577532abc54dafa60d0d6cfc74fd2 (diff) | |
| download | riscv-opcodes-b6747a260e225c3eacc354335e7f12ff4b7b1f3e.zip riscv-opcodes-b6747a260e225c3eacc354335e7f12ff4b7b1f3e.tar.gz riscv-opcodes-b6747a260e225c3eacc354335e7f12ff4b7b1f3e.tar.bz2 | |
Update SPTBR fields
| -rw-r--r-- | encoding.h | 23 |
1 files changed, 9 insertions, 14 deletions
@@ -106,26 +106,19 @@ #define PRV_H 2 #define PRV_M 3 -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 - #define SPTBR32_MODE 0x80000000 #define SPTBR32_ASID 0x7FC00000 #define SPTBR32_PPN 0x003FFFFF -#define SPTBR64_MODE 0xE000000000000000 -#define SPTBR64_ASID 0x1FFFE00000000000 -#define SPTBR64_PPN 0x0000003FFFFFFFFF +#define SPTBR64_MODE 0xF000000000000000 +#define SPTBR64_ASID 0x0FFFF00000000000 +#define SPTBR64_PPN 0x00000FFFFFFFFFFF #define SPTBR_MODE_OFF 0 #define SPTBR_MODE_SV32 1 -#define SPTBR_MODE_SV39 4 -#define SPTBR_MODE_SV48 5 -#define SPTBR_MODE_SV57 6 -#define SPTBR_MODE_SV64 7 +#define SPTBR_MODE_SV39 8 +#define SPTBR_MODE_SV48 9 +#define SPTBR_MODE_SV57 10 +#define SPTBR_MODE_SV64 11 #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 @@ -167,10 +160,12 @@ # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVEL_BITS 9 +# define SPTBR_MODE SPTBR64_MODE #else # define MSTATUS_SD MSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVEL_BITS 10 +# define SPTBR_MODE SPTBR32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) |