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| author | Andrew Waterman <andrew@sifive.com> | 2018-08-27 16:34:47 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-06 17:56:30 -0800 |
| commit | 835b8658e12ac2374598a086b542a4d564c6ed45 (patch) | |
| tree | dbd9468236c037ac167f0cf875ad869bea1e79ad | |
| parent | 3bdfd90a9ad8be6d2d8f528a5d0543b6600bde1d (diff) | |
| download | riscv-opcodes-835b8658e12ac2374598a086b542a4d564c6ed45.zip riscv-opcodes-835b8658e12ac2374598a086b542a4d564c6ed45.tar.gz riscv-opcodes-835b8658e12ac2374598a086b542a4d564c6ed45.tar.bz2 | |
Split V table from rest of table
Generate it with the command
cat opcodes-v | ./parse-opcodes -vtex
| -rwxr-xr-x | parse-opcodes | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/parse-opcodes b/parse-opcodes index 1a5e263..eeae739 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -919,8 +919,9 @@ def make_latex_table(): print_subtitle('RV64D Standard Extension (in addition to RV32D)') print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d') print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x') - print_footer() + print_footer('\\caption{Instruction listing for RISC-V}') +def make_vector_latex_table(): print_vector_header() print_subtitle('RV32V Standard Extension', 9) print_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor') @@ -1089,6 +1090,8 @@ for line in sys.stdin: if sys.argv[1] == '-tex': make_latex_table() +elif sys.argv[1] == '-vtex': + make_vector_latex_table() elif sys.argv[1] == '-privtex': make_supervisor_latex_table() elif sys.argv[1] == '-chisel': |