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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-25 23:26:00 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-25 23:26:00 -0700 |
| commit | 7d22c8896f4a7b50f2a1f8d902aea76ad66c4e47 (patch) | |
| tree | 9df573dca29f382f7ffd3403d1d22be510f4b975 | |
| parent | 1a25601e9bbc2a0ab49203ef7a0b6d5a44c4b658 (diff) | |
| download | riscv-opcodes-7d22c8896f4a7b50f2a1f8d902aea76ad66c4e47.zip riscv-opcodes-7d22c8896f4a7b50f2a1f8d902aea76ad66c4e47.tar.gz riscv-opcodes-7d22c8896f4a7b50f2a1f8d902aea76ad66c4e47.tar.bz2 | |
Re-rename trigger registers to be 1-based
| -rwxr-xr-x | parse-opcodes | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/parse-opcodes b/parse-opcodes index ba32f6a..c0809cc 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -93,9 +93,9 @@ csrs = [ (0x705, 'mstime_delta'), (0x706, 'msinstret_delta'), (0x7a0, 'tselect'), - (0x7a1, 'tdata0'), - (0x7a2, 'tdata1'), - (0x7a3, 'tdata2'), + (0x7a1, 'tdata1'), + (0x7a2, 'tdata2'), + (0x7a3, 'tdata3'), (0x7b0, 'dcsr'), (0x7b1, 'dpc'), (0x7b2, 'dscratch'), |