diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:40:36 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-09 12:40:36 -0800 |
| commit | 2536e5268c031d734e2334e4d9afde1b8517db1b (patch) | |
| tree | 5b9a283b9cd50a9235dc9e0a08aed281091afcf7 | |
| parent | b6747a260e225c3eacc354335e7f12ff4b7b1f3e (diff) | |
| download | riscv-opcodes-2536e5268c031d734e2334e4d9afde1b8517db1b.zip riscv-opcodes-2536e5268c031d734e2334e4d9afde1b8517db1b.tar.gz riscv-opcodes-2536e5268c031d734e2334e4d9afde1b8517db1b.tar.bz2 | |
New counter-enable mechanism
| -rwxr-xr-x | parse-opcodes | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/parse-opcodes b/parse-opcodes index 3818309..be88241 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -90,6 +90,7 @@ csrs = [ (0x100, 'sstatus'), (0x104, 'sie'), (0x105, 'stvec'), + (0x106, 'scounteren'), (0x140, 'sscratch'), (0x141, 'sepc'), (0x142, 'scause'), @@ -104,6 +105,7 @@ csrs = [ (0x303, 'mideleg'), (0x304, 'mie'), (0x305, 'mtvec'), + (0x306, 'mcounteren'), (0x340, 'mscratch'), (0x341, 'mepc'), (0x342, 'mcause'), @@ -147,8 +149,6 @@ csrs = [ (0xB1D, 'mhpmcounter29'), (0xB1E, 'mhpmcounter30'), (0xB1F, 'mhpmcounter31'), - (0x320, 'mucounteren'), - (0x321, 'mscounteren'), (0x323, 'mhpmevent3'), (0x324, 'mhpmevent4'), (0x325, 'mhpmevent5'), |