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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-18 17:55:19 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-18 17:56:46 -0700 |
| commit | 10b49ea88ec38f00c040090b6adb733e976f5b48 (patch) | |
| tree | 1c669010fcac6934c34f84000df84821706c8a59 | |
| parent | 6f4761cb88e31f2214b07b968736cb1df3733ecb (diff) | |
| download | riscv-opcodes-10b49ea88ec38f00c040090b6adb733e976f5b48.zip riscv-opcodes-10b49ea88ec38f00c040090b6adb733e976f5b48.tar.gz riscv-opcodes-10b49ea88ec38f00c040090b6adb733e976f5b48.tar.bz2 | |
Add README
Closes #6
| -rw-r--r-- | README.md | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/README.md b/README.md new file mode 100644 index 0000000..bb981ea --- /dev/null +++ b/README.md @@ -0,0 +1,10 @@ +riscv-opcodes +=========================================================================== + +This repo enumerates standard RISC-V instruction opcodes and control and +status registers. It also contains a script to convert them into several +formats (C, Scala, LaTeX). + +This repo is not meant to stand alone; it is a subcomponent of +[riscv-tools](https://github.com/riscv/riscv-tools) and assumes that it +is part of that directory structure. |