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| author | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-29 12:11:47 -0700 |
|---|---|---|
| committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-29 19:16:39 -0700 |
| commit | c948773153456578e216a1218d6d1a88571769e8 (patch) | |
| tree | 84a930b45c6cc2eb39a1eb5f735e597533dc0290 | |
| parent | dd3bbcd0ed4d7c86938c5c8b4ed32ecfeb11ee04 (diff) | |
| download | riscv-opcodes-c948773153456578e216a1218d6d1a88571769e8.zip riscv-opcodes-c948773153456578e216a1218d6d1a88571769e8.tar.gz riscv-opcodes-c948773153456578e216a1218d6d1a88571769e8.tar.bz2 | |
add unary negation operation
| -rw-r--r-- | opcodes-v | 1 | ||||
| -rwxr-xr-x | parse-opcodes | 2 |
2 files changed, 2 insertions, 1 deletions
@@ -166,6 +166,7 @@ vselect m vd vs1 vs2 27..25=2 31..28=12 14=1 6..0=0x57 vclass m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=0 vpopc m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=1 vsqrt m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=2 +vneg m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=3 vredsum m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=4 vredmax m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=5 vredmin m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=6 diff --git a/parse-opcodes b/parse-opcodes index 1bdf8ae..6722219 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -953,7 +953,7 @@ def make_latex_table(): def make_vector_adoc_table(): #print_vec_subtitile('RV32V Standard Extension') print_vec_header() - print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor') + print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor', 'vneg') print_vec_insts('vseq', 'vsne', 'vslt', 'vsge', 'vsltu', 'vsgeu') print_vec_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide', 'vrgather') print_vec_insts('vdiv', 'vrem', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu') |