From c948773153456578e216a1218d6d1a88571769e8 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 29 Oct 2018 12:11:47 -0700 Subject: add unary negation operation --- opcodes-v | 1 + parse-opcodes | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/opcodes-v b/opcodes-v index 051f2b8..6a55ae6 100644 --- a/opcodes-v +++ b/opcodes-v @@ -166,6 +166,7 @@ vselect m vd vs1 vs2 27..25=2 31..28=12 14=1 6..0=0x57 vclass m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=0 vpopc m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=1 vsqrt m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=2 +vneg m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=3 vredsum m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=4 vredmax m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=5 vredmin m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=6 diff --git a/parse-opcodes b/parse-opcodes index 1bdf8ae..6722219 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -953,7 +953,7 @@ def make_latex_table(): def make_vector_adoc_table(): #print_vec_subtitile('RV32V Standard Extension') print_vec_header() - print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor') + print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor', 'vneg') print_vec_insts('vseq', 'vsne', 'vslt', 'vsge', 'vsltu', 'vsgeu') print_vec_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide', 'vrgather') print_vec_insts('vdiv', 'vrem', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu') -- cgit v1.1