diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-18 00:55:07 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-28 00:10:23 -0800 |
| commit | 90a3e36cebd260e5383db2e6a939748968848fec (patch) | |
| tree | a129744197ded630467a92ba79e7fde7abd7a241 | |
| parent | 2b3905ed85371cc4cecb58730ae34502708de701 (diff) | |
| download | riscv-opcodes-90a3e36cebd260e5383db2e6a939748968848fec.zip riscv-opcodes-90a3e36cebd260e5383db2e6a939748968848fec.tar.gz riscv-opcodes-90a3e36cebd260e5383db2e6a939748968848fec.tar.bz2 | |
rvv: add vleb csr register and mstatus.vs field
1. vleb is read-only CSR to keep vector implementation lenght in byte
2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension
state
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | encoding.h | 2 | ||||
| -rwxr-xr-x | parse_opcodes | 1 |
2 files changed, 3 insertions, 0 deletions
@@ -22,6 +22,7 @@ #define MSTATUS_TVM 0x00100000 #define MSTATUS_TW 0x00200000 #define MSTATUS_TSR 0x00400000 +#define MSTATUS_VS 0x01800000 #define MSTATUS32_SD 0x80000000 #define MSTATUS_UXL 0x0000000300000000 #define MSTATUS_SXL 0x0000000C00000000 @@ -36,6 +37,7 @@ #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 #define SSTATUS_MXR 0x00080000 +#define SSTATUS_VS 0x01800000 #define SSTATUS32_SD 0x80000000 #define SSTATUS_UXL 0x0000000300000000 #define SSTATUS64_SD 0x8000000000000000 diff --git a/parse_opcodes b/parse_opcodes index 9ac586e..883b953 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -118,6 +118,7 @@ csrs = [ (0xC1F, 'hpmcounter31'), (0xC20, 'vl'), (0xC21, 'vtype'), + (0xC22, 'vlenb'), # Standard Supervisor R/W (0x100, 'sstatus'), |