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| author | Andrew Waterman <andrew@sifive.com> | 2020-05-12 00:54:56 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-05-12 00:54:56 -0700 |
| commit | 8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275 (patch) | |
| tree | ed84df9d8a71eeef4117eb6c3ac8cc605853e610 | |
| parent | 36712402c3000db1b897cf2c021fb28f860262ad (diff) | |
| download | riscv-opcodes-8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275.zip riscv-opcodes-8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275.tar.gz riscv-opcodes-8489e25c98d9b3ab0bcb6efb2e93bcc45a0d7275.tar.bz2 | |
RVV v0.9: change vl1r/vs1r opcodes
https://github.com/riscv/riscv-v-spec/commit/5a0911c56394cc9ae2b5ade60a019cc82b2f926a
| -rw-r--r-- | opcodes-rvv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index c2da983..97af0fb 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -74,8 +74,8 @@ vlwuff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 # Vector Load/Store Whole Registers # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions -vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vs1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vs3 6..0=0x27 +vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vs1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 # Vector Floating-Point Instructions # https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions |