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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-15 13:55:28 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-15 13:55:28 -0800 |
| commit | 51b41643bd3ac801e168c9ed0b325b35aaea609a (patch) | |
| tree | b1be7cd44f3485d643e586b5dc9f8756fc941d18 | |
| parent | cd448c3047f541657b8a0efb76d6213380ef741b (diff) | |
| download | riscv-opcodes-51b41643bd3ac801e168c9ed0b325b35aaea609a.zip riscv-opcodes-51b41643bd3ac801e168c9ed0b325b35aaea609a.tar.gz riscv-opcodes-51b41643bd3ac801e168c9ed0b325b35aaea609a.tar.bz2 | |
Add vaaddu/vasubu; change vaadd/vasub opcodes
See https://github.com/riscv/riscv-v-spec/commit/c2f3157e34d3a0f77ccbbc502bdf1530da17aba8
| -rw-r--r-- | opcodes-rvv | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index bf8c3e2..d6deb12 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -214,9 +214,7 @@ vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vaadd.vx 31..26=0x24 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vasub.vx 31..26=0x26 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 @@ -261,9 +259,7 @@ vsaddu.vv 31..26=0x20 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsadd.vv 31..26=0x21 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vssubu.vv 31..26=0x22 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vssub.vv 31..26=0x23 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vaadd.vv 31..26=0x24 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsll.vv 31..26=0x25 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 -vasub.vv 31..26=0x26 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsmul.vv 31..26=0x27 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsrl.vv 31..26=0x28 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 vsra.vv 31..26=0x29 vm vs2 rs1 14..12=0x0 vd 6..0=0x57 @@ -305,7 +301,6 @@ vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vaadd.vi 31..26=0x24 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 @@ -325,6 +320,11 @@ vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 vd 6..0=0x57 vcompress.vm 31..26=0x17 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 @@ -374,6 +374,11 @@ vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # OPMVX +vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 |