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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-28 01:14:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-28 01:14:05 -0700 |
| commit | 231c5d58940113b006aa9fa22f47c18d5fac4123 (patch) | |
| tree | 712b8350c02f512f7e967e15b6c2df2580ed7bda | |
| parent | 9d4e22de020069d9cc3624509955d5fcd662482b (diff) | |
| download | riscv-opcodes-231c5d58940113b006aa9fa22f47c18d5fac4123.zip riscv-opcodes-231c5d58940113b006aa9fa22f47c18d5fac4123.tar.gz riscv-opcodes-231c5d58940113b006aa9fa22f47c18d5fac4123.tar.bz2 | |
Add FP->int truncating conversions
See https://github.com/riscv/riscv-v-spec/pull/403/
| -rw-r--r-- | opcodes-rvv | 40 |
1 files changed, 23 insertions, 17 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 10277a2..9d9cf99 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -153,23 +153,29 @@ vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfcvt.xu.f.v 31..26=0x22 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 -vfcvt.x.f.v 31..26=0x22 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 -vfcvt.f.xu.v 31..26=0x22 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 -vfcvt.f.x.v 31..26=0x22 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 - -vfwcvt.xu.f.v 31..26=0x22 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 -vfwcvt.x.f.v 31..26=0x22 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.xu.v 31..26=0x22 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.x.v 31..26=0x22 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.f.v 31..26=0x22 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 - -vfncvt.xu.f.w 31..26=0x22 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 -vfncvt.x.f.w 31..26=0x22 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 -vfncvt.f.xu.w 31..26=0x22 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 -vfncvt.f.x.w 31..26=0x22 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 -vfncvt.f.f.w 31..26=0x22 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 -vfncvt.rod.f.f.w 31..26=0x22 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 +vfcvt.xu.f.v 31..26=0x22 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfcvt.x.f.v 31..26=0x22 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 +vfcvt.f.xu.v 31..26=0x22 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 +vfcvt.f.x.v 31..26=0x22 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.xu.f.v 31..26=0x22 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.x.f.v 31..26=0x22 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 + +vfwcvt.xu.f.v 31..26=0x22 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 +vfwcvt.x.f.v 31..26=0x22 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.xu.v 31..26=0x22 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.x.v 31..26=0x22 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.f.v 31..26=0x22 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.xu.f.v 31..26=0x22 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.x.f.v 31..26=0x22 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 + +vfncvt.xu.f.w 31..26=0x22 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 +vfncvt.x.f.w 31..26=0x22 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 +vfncvt.f.xu.w 31..26=0x22 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 +vfncvt.f.x.w 31..26=0x22 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 +vfncvt.f.f.w 31..26=0x22 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 +vfncvt.rod.f.f.w 31..26=0x22 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.xu.f.w 31..26=0x22 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.x.f.w 31..26=0x22 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 vfsqrt.v 31..26=0x23 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 vfclass.v 31..26=0x23 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 |