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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-03 18:44:45 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-03 18:44:45 -0800 |
| commit | 0ce3ec1f7d82d5449ba5d00302270076f6cc34f6 (patch) | |
| tree | 1189f43367842a03c24e6d4f47312863f3431b8f | |
| parent | c7e17632237219090791ba67dd700c2fca432e20 (diff) | |
| download | riscv-opcodes-0ce3ec1f7d82d5449ba5d00302270076f6cc34f6.zip riscv-opcodes-0ce3ec1f7d82d5449ba5d00302270076f6cc34f6.tar.gz riscv-opcodes-0ce3ec1f7d82d5449ba5d00302270076f6cc34f6.tar.bz2 | |
Factor out RVC opcodes into per-extension files
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | opcodes-rv128c | 6 | ||||
| -rw-r--r-- | opcodes-rv32c | 5 | ||||
| -rw-r--r-- | opcodes-rv64c | 14 | ||||
| -rw-r--r-- | opcodes-rvc | 11 | ||||
| -rw-r--r-- | opcodes-rvc-pseudo | 26 |
6 files changed, 37 insertions, 31 deletions
@@ -6,11 +6,11 @@ ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv128q opcodes-system -ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-custom opcodes-rvv +ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-rv128c opcodes-custom opcodes-rvv -ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvc-pseudo opcodes-rvv-pseudo +ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo -install: $(ISASIM_H) inst.chisel instr-table.tex priv-instr-table.tex +install: $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse_opcodes encoding.h cp encoding.h $@ diff --git a/opcodes-rv128c b/opcodes-rv128c new file mode 100644 index 0000000..dddb992 --- /dev/null +++ b/opcodes-rv128c @@ -0,0 +1,6 @@ +# RV128C additions to RVC + +@c.lq 1..0=0 15..13=1 12=ignore 11..2=ignore # c.fld for RV32/64 +@c.sq 1..0=0 15..13=5 12=ignore 11..2=ignore # c.fsd for RV32/64 +@c.lqsp 1..0=2 15..13=1 12=ignore 11..2=ignore # c.fldsp for RV32/64 +@c.sqsp 1..0=2 15..13=5 12=ignore 11..2=ignore # c.fsdsp for RV32/64 diff --git a/opcodes-rv32c b/opcodes-rv32c new file mode 100644 index 0000000..d91f288 --- /dev/null +++ b/opcodes-rv32c @@ -0,0 +1,5 @@ +# RV32C additions to RVC + +@c.srli.rv32 1..0=1 15..13=4 12=0 11..10=0 9..2=ignore +@c.srai.rv32 1..0=1 15..13=4 12=0 11..10=1 9..2=ignore +@c.slli.rv32 1..0=2 15..13=0 12=0 11..2=ignore diff --git a/opcodes-rv64c b/opcodes-rv64c new file mode 100644 index 0000000..7efc7c5 --- /dev/null +++ b/opcodes-rv64c @@ -0,0 +1,14 @@ +# RV64C additions to RVC + +# C0 encoding space +@c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32 +@c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32 + +# C1 encoding space +c.subw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore +c.addw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore +@c.addiw 1..0=1 15..13=1 12=ignore 11..2=ignore # c.jal for RV32 + +# C2 encoding space +@c.ldsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.flwsp for RV32 +@c.sdsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.fswsp for RV32 diff --git a/opcodes-rvc b/opcodes-rvc index af5dbff..64fc19a 100644 --- a/opcodes-rvc +++ b/opcodes-rvc @@ -1,5 +1,14 @@ # compressed instructions +# these aren't really pseudo-ops, but they overlay other encodings, +# so they are here to prevent parse_opcodes from barfing + +@c.nop 1..0=1 15..13=0 12=0 11..7=0 6..2=0 +@c.addi16sp 1..0=1 15..13=3 12=ignore 11..7=2 6..2=ignore +@c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0 +@c.jalr 1..0=2 15..13=4 12=1 11..7=ignore 6..2=0 +@c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 + # C0 encoding space c.addi4spn 1..0=0 15..13=0 12=ignore 11..2=ignore c.fld 1..0=0 15..13=1 12=ignore 11..2=ignore # c.lq for RV128 @@ -21,8 +30,6 @@ c.sub 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=0 4..2=ignore c.xor 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=1 4..2=ignore c.or 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=2 4..2=ignore c.and 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=3 4..2=ignore -c.subw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.addw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore c.j 1..0=1 15..13=5 12=ignore 11..2=ignore c.beqz 1..0=1 15..13=6 12=ignore 11..2=ignore c.bnez 1..0=1 15..13=7 12=ignore 11..2=ignore diff --git a/opcodes-rvc-pseudo b/opcodes-rvc-pseudo deleted file mode 100644 index 57ed05c..0000000 --- a/opcodes-rvc-pseudo +++ /dev/null @@ -1,26 +0,0 @@ -# these aren't really pseudo-ops, but they overlay other encodings, -# so they are here to prevent parse_opcodes from barfing - -@c.nop 1..0=1 15..13=0 12=0 11..7=0 6..2=0 -@c.addi16sp 1..0=1 15..13=3 12=ignore 11..7=2 6..2=ignore -@c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0 -@c.jalr 1..0=2 15..13=4 12=1 11..7=ignore 6..2=0 -@c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 - -# RV32C -@c.srli.rv32 1..0=1 15..13=4 12=0 11..10=0 9..2=ignore -@c.srai.rv32 1..0=1 15..13=4 12=0 11..10=1 9..2=ignore -@c.slli.rv32 1..0=2 15..13=0 12=0 11..2=ignore - -# RV64C -@c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32 -@c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32 -@c.addiw 1..0=1 15..13=1 12=ignore 11..2=ignore # c.jal for RV32 -@c.ldsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.flwsp for RV32 -@c.sdsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.fswsp for RV32 - -# RV128C -@c.lq 1..0=0 15..13=1 12=ignore 11..2=ignore # c.fld for RV32/64 -@c.sq 1..0=0 15..13=5 12=ignore 11..2=ignore # c.fsd for RV32/64 -@c.lqsp 1..0=2 15..13=1 12=ignore 11..2=ignore # c.fldsp for RV32/64 -@c.sqsp 1..0=2 15..13=5 12=ignore 11..2=ignore # c.fsdsp for RV32/64 |