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authorAndrew Waterman <waterman@eecs.berkeley.edu>2013-11-25 01:43:47 -0800
committerAndrew Waterman <waterman@eecs.berkeley.edu>2013-11-25 01:43:47 -0800
commit2d11bac94537e08b30b8ace0eb39ecbbbc386c8e (patch)
tree5c9b9dcee1a2fe0e2fb666020d552a207daa8958
parentbc445390566f8831dd8bb34bcc05d80c7401296a (diff)
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New privileged ISA
-rw-r--r--Makefile35
-rw-r--r--encoding.h101
-rw-r--r--inst.chisel114
-rw-r--r--instr-table.tex86
-rw-r--r--opcodes71
-rw-r--r--opcodes-custom48
-rw-r--r--opcodes-hwacha-pseudo60
-rw-r--r--opcodes-pseudo10
-rwxr-xr-xparse-opcodes86
9 files changed, 433 insertions, 178 deletions
diff --git a/Makefile b/Makefile
index c2b134f..20d430f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,31 +1,24 @@
-ISASIM_H := ../riscv-isa-sim/riscv/opcodes.h
-PK_H := ../riscv-pk/pk/riscv-opc.h
+ISASIM_H := ../riscv-isa-sim/riscv/encoding.h
+PK_H := ../riscv-pk/pk/encoding.h
+ENV_H := ../riscv-tests/env/encoding.h
GAS_H := ../riscv-gcc/binutils-2.21.1/include/opcode/riscv-opc.h
XCC_H := ../riscv-gcc/gcc-4.6.1/gcc/config/riscv/riscv-opc.h
-install: $(ISASIM_H) $(PK_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex
+ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-custom
-$(ISASIM_H): opcodes parse-opcodes
- ./parse-opcodes -isasim < $< > $@
+install: $(ISASIM_H) $(PK_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex
-$(PK_H): opcodes parse-opcodes
- ./parse-opcodes -disasm < $< > $@
+$(ISASIM_H) $(PK_H) $(ENV_H): $(ALL_OPCODES) parse-opcodes
+ cp encoding.h $@
+ cat opcodes | ./parse-opcodes -c >> $@
-$(GAS_H): opcodes opcodes-hwacha opcodes-rvc opcodes-custom parse-opcodes
- ./parse-opcodes -disasm < $< > $@
- ./parse-opcodes -disasm < opcodes-rvc >> $@
- ./parse-opcodes -disasm < opcodes-custom >> $@
- ./parse-opcodes -disasm < opcodes-hwacha >> $@
- ./parse-opcodes -disasm < opcodes-hwacha-pseudo >> $@
+$(GAS_H) $(XCC_H): $(ALL_OPCODES) parse-opcodes
+ cat $(ALL_OPCODES) | ./parse-opcodes -c > $@
-$(XCC_H): opcodes parse-opcodes
- ./parse-opcodes -disasm < $< > $@
+inst.chisel: $(ALL_OPCODES) parse-opcodes
+ cat opcodes opcodes-custom | ./parse-opcodes -chisel > $@
-inst.chisel: opcodes parse-opcodes
- ./parse-opcodes -chisel < $< > $@
- ./parse-opcodes -chisel < opcodes-custom >> $@
-
-instr-table.tex: opcodes parse-opcodes
- ./parse-opcodes -tex < $< > $@
+instr-table.tex: $(ALL_OPCODES) parse-opcodes
+ cat opcodes opcodes-pseudo | ./parse-opcodes -tex > $@
.PHONY : install
diff --git a/encoding.h b/encoding.h
new file mode 100644
index 0000000..a5467e0
--- /dev/null
+++ b/encoding.h
@@ -0,0 +1,101 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define SR_S 0x00000001
+#define SR_PS 0x00000002
+#define SR_EI 0x00000004
+#define SR_PEI 0x00000008
+#define SR_EF 0x00000010
+#define SR_U64 0x00000020
+#define SR_S64 0x00000040
+#define SR_VM 0x00000080
+#define SR_EA 0x00000100
+#define SR_IM 0x00FF0000
+#define SR_IP 0xFF000000
+#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
+#define SR_IM_SHIFT 16
+#define SR_IP_SHIFT 24
+
+#define IRQ_COP 2
+#define IRQ_IPI 5
+#define IRQ_HOST 6
+#define IRQ_TIMER 7
+
+#define IMPL_SPIKE 1
+#define IMPL_ROCKET 2
+
+#define CAUSE_MISALIGNED_FETCH 0
+#define CAUSE_FAULT_FETCH 1
+#define CAUSE_ILLEGAL_INSTRUCTION 2
+#define CAUSE_PRIVILEGED_INSTRUCTION 3
+#define CAUSE_FP_DISABLED 4
+#define CAUSE_SYSCALL 6
+#define CAUSE_BREAKPOINT 7
+#define CAUSE_MISALIGNED_LOAD 8
+#define CAUSE_MISALIGNED_STORE 9
+#define CAUSE_FAULT_LOAD 10
+#define CAUSE_FAULT_STORE 11
+#define CAUSE_ACCELERATOR_DISABLED 12
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Entry is a page Table descriptor
+#define PTE_T 0x002 // Entry is a page Table, not a terminal node
+#define PTE_G 0x004 // Global
+#define PTE_UR 0x008 // User Write permission
+#define PTE_UW 0x010 // User Read permission
+#define PTE_UX 0x020 // User eXecute permission
+#define PTE_SR 0x040 // Supervisor Read permission
+#define PTE_SW 0x080 // Supervisor Write permission
+#define PTE_SX 0x100 // Supervisor eXecute permission
+#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define RISCV_PGLEVELS 3
+# define RISCV_PGSHIFT 13
+#else
+# define RISCV_PGLEVELS 2
+# define RISCV_PGSHIFT 12
+#endif
+#define RISCV_PGLEVEL_BITS 10
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#define read_csr(reg) ({ long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val))
+
+#define swap_csr(reg, val) ({ long __tmp; \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ long __tmp; \
+ if (__builtin_constant_p(bit) && (bit) < 32) \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ long __tmp; \
+ if (__builtin_constant_p(bit) && (bit) < 32) \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define rdcycle() ({ unsigned long __tmp; \
+ asm volatile ("rdcycle %0" : "=r"(__tmp)); \
+ __tmp; })
+
+#endif
+
+#endif
+
+#endif
diff --git a/inst.chisel b/inst.chisel
index abda1c6..1b22a3e 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -1,4 +1,5 @@
- /* Automatically generated by parse-opcodes */
+/* Automatically generated by parse-opcodes */
+object Instructions {
def JAL = Bits("b?????????????????????????1100111")
def JALR = Bits("b?????????????????000?????1101111")
def BEQ = Bits("b?????????????????000?????1100011")
@@ -28,14 +29,6 @@
def SRA = Bits("b0100000??????????101?????0110011")
def OR = Bits("b0000000??????????110?????0110011")
def AND = Bits("b0000000??????????111?????0110011")
- def MUL = Bits("b0000001??????????000?????0110011")
- def MULH = Bits("b0000001??????????001?????0110011")
- def MULHSU = Bits("b0000001??????????010?????0110011")
- def MULHU = Bits("b0000001??????????011?????0110011")
- def DIV = Bits("b0000001??????????100?????0110011")
- def DIVU = Bits("b0000001??????????101?????0110011")
- def REM = Bits("b0000001??????????110?????0110011")
- def REMU = Bits("b0000001??????????111?????0110011")
def ADDIW = Bits("b?????????????????000?????0011011")
def SLLIW = Bits("b0000000??????????001?????0011011")
def SRLIW = Bits("b0000000??????????101?????0011011")
@@ -45,11 +38,6 @@
def SLLW = Bits("b0000000??????????001?????0111011")
def SRLW = Bits("b0000000??????????101?????0111011")
def SRAW = Bits("b0100000??????????101?????0111011")
- def MULW = Bits("b0000001??????????000?????0111011")
- def DIVW = Bits("b0000001??????????100?????0111011")
- def DIVUW = Bits("b0000001??????????101?????0111011")
- def REMW = Bits("b0000001??????????110?????0111011")
- def REMUW = Bits("b0000001??????????111?????0111011")
def LB = Bits("b?????????????????000?????0000011")
def LH = Bits("b?????????????????001?????0000011")
def LW = Bits("b?????????????????010?????0000011")
@@ -61,6 +49,21 @@
def SH = Bits("b?????????????????001?????0100011")
def SW = Bits("b?????????????????010?????0100011")
def SD = Bits("b?????????????????011?????0100011")
+ def FENCE = Bits("b?????????????????000?????0001111")
+ def FENCE_I = Bits("b?????????????????001?????0001111")
+ def MUL = Bits("b0000001??????????000?????0110011")
+ def MULH = Bits("b0000001??????????001?????0110011")
+ def MULHSU = Bits("b0000001??????????010?????0110011")
+ def MULHU = Bits("b0000001??????????011?????0110011")
+ def DIV = Bits("b0000001??????????100?????0110011")
+ def DIVU = Bits("b0000001??????????101?????0110011")
+ def REM = Bits("b0000001??????????110?????0110011")
+ def REMU = Bits("b0000001??????????111?????0110011")
+ def MULW = Bits("b0000001??????????000?????0111011")
+ def DIVW = Bits("b0000001??????????100?????0111011")
+ def DIVUW = Bits("b0000001??????????101?????0111011")
+ def REMW = Bits("b0000001??????????110?????0111011")
+ def REMUW = Bits("b0000001??????????111?????0111011")
def AMOADD_W = Bits("b00000????????????010?????0101111")
def AMOXOR_W = Bits("b00100????????????010?????0101111")
def AMOOR_W = Bits("b01000????????????010?????0101111")
@@ -83,18 +86,15 @@
def AMOSWAP_D = Bits("b00001????????????011?????0101111")
def LR_D = Bits("b00010??00000?????011?????0101111")
def SC_D = Bits("b00011????????????011?????0101111")
- def FENCE = Bits("b?????????????????000?????0001111")
- def FENCE_I = Bits("b?????????????????001?????0001111")
- def SYSCALL = Bits("b00000000000000000000000001110111")
- def BREAK = Bits("b00000000000000000001000001110111")
- def RDCYCLE = Bits("b00000000000000000100?????1110111")
- def RDTIME = Bits("b00000010000000000100?????1110111")
- def RDINSTRET = Bits("b00000100000000000100?????1110111")
- def MTPCR = Bits("b0000000??????????000?????1110011")
- def MFPCR = Bits("b000000000000?????001?????1110011")
- def SETPCR = Bits("b?????????????????010?????1110011")
- def CLEARPCR = Bits("b?????????????????011?????1110011")
- def ERET = Bits("b00000000000000000100000001110011")
+ def SCALL = Bits("b00000000000000000000000001110011")
+ def SBREAK = Bits("b00000000000100000000000001110011")
+ def SRET = Bits("b10000000000000000000000001110011")
+ def CSRRW = Bits("b?????????????????001?????1110011")
+ def CSRRS = Bits("b?????????????????010?????1110011")
+ def CSRRC = Bits("b?????????????????011?????1110011")
+ def CSRRWI = Bits("b?????????????????101?????1110011")
+ def CSRRSI = Bits("b?????????????????110?????1110011")
+ def CSRRCI = Bits("b?????????????????111?????1110011")
def FADD_S = Bits("b0000000??????????????????1010011")
def FSUB_S = Bits("b0000100??????????????????1010011")
def FMUL_S = Bits("b0001000??????????????????1010011")
@@ -141,10 +141,8 @@
def FMAX_D = Bits("b1100101??????????000?????1010011")
def FMV_X_S = Bits("b111000000000?????000?????1010011")
def FMV_X_D = Bits("b111000100000?????000?????1010011")
- def FRSR = Bits("b11101000000000000000?????1010011")
def FMV_S_X = Bits("b111100000000?????000?????1010011")
def FMV_D_X = Bits("b111100100000?????000?????1010011")
- def FSSR = Bits("b111110000000?????000?????1010011")
def FLW = Bits("b?????????????????010?????0000111")
def FLD = Bits("b?????????????????011?????0000111")
def FSW = Bits("b?????????????????010?????0100111")
@@ -157,7 +155,6 @@
def FMSUB_D = Bits("b?????01??????????????????1000111")
def FNMSUB_D = Bits("b?????01??????????????????1001011")
def FNMADD_D = Bits("b?????01??????????????????1001111")
- /* Automatically generated by parse-opcodes */
def CUSTOM0 = Bits("b?????????????????000?????0001011")
def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011")
def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011")
@@ -182,3 +179,62 @@
def CUSTOM3_RD = Bits("b?????????????????100?????1111011")
def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011")
def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
+}
+object CSRs {
+ val sup0 = 1280
+ val fflags = 1
+ val frm = 2
+ val fcsr = 3
+ val cycle = 4
+ val time = 5
+ val instret = 6
+ val sup1 = 1281
+ val evec = 1288
+ val cause = 1289
+ val status = 1290
+ val hartid = 1291
+ val impl = 1292
+ val epc = 1282
+ val send_ipi = 1294
+ val clear_ipi = 1295
+ val badvaddr = 1283
+ val ptbr = 1284
+ val stats = 1308
+ val reset = 1309
+ val tohost = 1310
+ val asid = 1285
+ val count = 1286
+ val compare = 1287
+ val fromhost = 1311
+ val fatc = 1293
+ val all = {
+ val res = collection.mutable.ArrayBuffer[Int]()
+ res += sup0
+ res += fflags
+ res += frm
+ res += fcsr
+ res += cycle
+ res += time
+ res += instret
+ res += sup1
+ res += evec
+ res += cause
+ res += status
+ res += hartid
+ res += impl
+ res += epc
+ res += send_ipi
+ res += clear_ipi
+ res += badvaddr
+ res += ptbr
+ res += stats
+ res += reset
+ res += tohost
+ res += asid
+ res += count
+ res += compare
+ res += fromhost
+ res += fatc
+ res.toArray
+ }
+}
diff --git a/instr-table.tex b/instr-table.tex
index 70d5157..4f2f5a8 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -457,47 +457,47 @@
\multicolumn{1}{c|}{00000} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{1110111} & SYSCALL \\
+\multicolumn{1}{c|}{1110011} & SCALL \\
\cline{2-11}
&
\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{2}{c|}{00001} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{001} &
+\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{1110111} & BREAK \\
+\multicolumn{1}{c|}{1110011} & SBREAK \\
\cline{2-11}
&
\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{2}{c|}{00100} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{100} &
+\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110111} & RDCYCLE rd \\
+\multicolumn{1}{c|}{1110011} & RDCYCLE rd \\
\cline{2-11}
&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00101} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{100} &
+\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110111} & RDTIME rd \\
+\multicolumn{1}{c|}{1110011} & RDTIME rd \\
\cline{2-11}
&
-\multicolumn{4}{|c|}{0000010} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00110} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{100} &
+\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110111} & RDINSTRET rd \\
+\multicolumn{1}{c|}{1110011} & RDINSTRET rd \\
\cline{2-11}
@@ -1435,22 +1435,62 @@
&
-\multicolumn{4}{|c|}{1111100} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00011} &
\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
+\multicolumn{1}{c|}{001} &
\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSSR rd,rs1 \\
+\multicolumn{1}{c|}{1110011} & FSSR rd,rs1 \\
\cline{2-11}
&
-\multicolumn{4}{|c|}{1110100} &
-\multicolumn{2}{c|}{00000} &
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00011} &
\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{000} &
+\multicolumn{1}{c|}{010} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & FRSR rd \\
+\cline{2-11}
+
+
+&
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00001} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{001} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & FSFLAGS rd,rs1 \\
+\cline{2-11}
+
+
+&
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00001} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & FRFLAGS rd \\
+\cline{2-11}
+
+
+&
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00010} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{001} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{1110011} & FSRM rd,rs1 \\
+\cline{2-11}
+
+
+&
+\multicolumn{4}{|c|}{0000000} &
+\multicolumn{2}{c|}{00010} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FRSR rd \\
+\multicolumn{1}{c|}{1110011} & FRRM rd \\
\cline{2-11}
diff --git a/opcodes b/opcodes
index 62efae9..53b1ce8 100644
--- a/opcodes
+++ b/opcodes
@@ -42,15 +42,6 @@ sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3
or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3
and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3
-mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3
-mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3
-mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3
-mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3
-div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3
-divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3
-rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3
-remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3
-
addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3
slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3
srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3
@@ -62,12 +53,6 @@ sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3
srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3
sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3
-mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3
-divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3
-divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3
-remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3
-remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3
-
lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3
lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3
lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3
@@ -81,6 +66,27 @@ sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3
sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3
sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3
+fence 31..28=ignore pred succ 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3
+fence.i 31..28=ignore 27..20=ignore 19..15=ignore 14..12=1 11..7=ignore 6..2=0x03 1..0=3
+
+# RV32M
+mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3
+mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3
+mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3
+mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3
+div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3
+divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3
+rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3
+remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3
+
+# RV64M
+mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3
+divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3
+divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3
+remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3
+remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3
+
+# RV32A
amoadd.w rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3
amoxor.w rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3
amoor.w rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3
@@ -92,7 +98,8 @@ amomaxu.w rd rs1 rs2 aqrl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3
amoswap.w rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3
lr.w rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3
sc.w rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3
-
+
+# RV64A
amoadd.d rd rs1 rs2 aqrl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3
amoxor.d rd rs1 rs2 aqrl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3
amoor.d rd rs1 rs2 aqrl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3
@@ -105,24 +112,18 @@ amoswap.d rd rs1 rs2 aqrl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3
lr.d rd rs1 24..20=0 aqrl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3
sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3
-fence 31..28=ignore pred succ 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3
-fence.i 31..28=ignore 27..20=ignore 19..15=ignore 14..12=1 11..7=ignore 6..2=0x03 1..0=3
-
-syscall 11..7=0 19..15=0 24..20=0 31..25=0 14..12=0 6..2=0x1D 1..0=3
-break 11..7=0 19..15=0 24..20=0 31..25=0 14..12=1 6..2=0x1D 1..0=3
-rdcycle rd 19..15=0 24..20=0 31..25=0 14..12=4 6..2=0x1D 1..0=3
-rdtime rd 19..15=0 24..20=0 31..25=1 14..12=4 6..2=0x1D 1..0=3
-rdinstret rd 19..15=0 24..20=0 31..25=2 14..12=4 6..2=0x1D 1..0=3
-
-# SUPERVISOR
-mtpcr rd rs1 rs2 31..25=0 14..12=0 6..2=0x1C 1..0=3
-mfpcr rd rs1 24..20=0 31..25=0 14..12=1 6..2=0x1C 1..0=3
-setpcr rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3
-clearpcr rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3
-eret 11..7=0 19..15=0 24..20=0 31..25=0 14..12=4 6..2=0x1C 1..0=3
-
-# 0x7C-0x7F are reserved for >32b instructions
-
+# SYSTEM
+scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
+sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
+sret 11..7=0 19..15=0 31..20=0x800 14..12=0 6..2=0x1C 1..0=3
+csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3
+csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3
+csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3
+csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3
+csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3
+csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3
+
+# F/D EXTENSIONS
fadd.s rd rs1 rs2 31..27=0x0 rm 26..25=0 6..2=0x14 1..0=3
fsub.s rd rs1 rs2 31..27=0x1 rm 26..25=0 6..2=0x14 1..0=3
fmul.s rd rs1 rs2 31..27=0x2 rm 26..25=0 6..2=0x14 1..0=3
@@ -180,10 +181,8 @@ fmax.d rd rs1 rs2 31..27=0x19 14..12=0 26..25=1 6..2=0x14 1..0=3
fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3
fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3
-frsr rd 19..15=0 24..20=0 31..27=0x1D 14..12=0 26..25=0 6..2=0x14 1..0=3
fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3
fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3
-fssr rd rs1 24..20=0 31..27=0x1F 14..12=0 26..25=0 6..2=0x14 1..0=3
flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3
fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3
diff --git a/opcodes-custom b/opcodes-custom
index 036bc4b..1df6f0f 100644
--- a/opcodes-custom
+++ b/opcodes-custom
@@ -1,27 +1,27 @@
-custom0 rd rs1 imm12 14..12=0 6..2=0x02 1..0=3
-custom0.rs1 rd rs1 imm12 14..12=2 6..2=0x02 1..0=3
-custom0.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x02 1..0=3
-custom0.rd rd rs1 imm12 14..12=4 6..2=0x02 1..0=3
-custom0.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x02 1..0=3
-custom0.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x02 1..0=3
+@custom0 rd rs1 imm12 14..12=0 6..2=0x02 1..0=3
+@custom0.rs1 rd rs1 imm12 14..12=2 6..2=0x02 1..0=3
+@custom0.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x02 1..0=3
+@custom0.rd rd rs1 imm12 14..12=4 6..2=0x02 1..0=3
+@custom0.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x02 1..0=3
+@custom0.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x02 1..0=3
-custom1 rd rs1 imm12 14..12=0 6..2=0x0A 1..0=3
-custom1.rs1 rd rs1 imm12 14..12=2 6..2=0x0A 1..0=3
-custom1.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x0A 1..0=3
-custom1.rd rd rs1 imm12 14..12=4 6..2=0x0A 1..0=3
-custom1.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x0A 1..0=3
-custom1.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x0A 1..0=3
+@custom1 rd rs1 imm12 14..12=0 6..2=0x0A 1..0=3
+@custom1.rs1 rd rs1 imm12 14..12=2 6..2=0x0A 1..0=3
+@custom1.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x0A 1..0=3
+@custom1.rd rd rs1 imm12 14..12=4 6..2=0x0A 1..0=3
+@custom1.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x0A 1..0=3
+@custom1.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x0A 1..0=3
-custom2 rd rs1 imm12 14..12=0 6..2=0x16 1..0=3
-custom2.rs1 rd rs1 imm12 14..12=2 6..2=0x16 1..0=3
-custom2.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x16 1..0=3
-custom2.rd rd rs1 imm12 14..12=4 6..2=0x16 1..0=3
-custom2.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x16 1..0=3
-custom2.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x16 1..0=3
+@custom2 rd rs1 imm12 14..12=0 6..2=0x16 1..0=3
+@custom2.rs1 rd rs1 imm12 14..12=2 6..2=0x16 1..0=3
+@custom2.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x16 1..0=3
+@custom2.rd rd rs1 imm12 14..12=4 6..2=0x16 1..0=3
+@custom2.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x16 1..0=3
+@custom2.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x16 1..0=3
-custom3 rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3
-custom3.rs1 rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3
-custom3.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3
-custom3.rd rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3
-custom3.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3
-custom3.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3
+@custom3 rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3
+@custom3.rs1 rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3
+@custom3.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3
+@custom3.rd rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3
+@custom3.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3
+@custom3.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3
diff --git a/opcodes-hwacha-pseudo b/opcodes-hwacha-pseudo
index ec70cfd..06466c7 100644
--- a/opcodes-hwacha-pseudo
+++ b/opcodes-hwacha-pseudo
@@ -5,42 +5,42 @@
# ---------------------------------------------------------------------------
# segment x/f s/u width xd xs1 xs2 opcode
# | | | | | | | |
-vld 31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlw 31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlwu 31..29=0 28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlh 31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlhu 31..29=0 28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlb 31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vlbu 31..29=0 28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vfld 31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
-vflw 31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vld 31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vlw 31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vlwu 31..29=0 28=0 27=1 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vlh 31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vlhu 31..29=0 28=0 27=1 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vlb 31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vlbu 31..29=0 28=0 27=1 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vfld 31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
+@vflw 31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x16 1..0=3
# segment x/f s/u width xd xs1 xs2 opcode
# | | | | | | | |
-vlstd 31..29=0 28=0 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlstw 31..29=0 28=0 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlstwu 31..29=0 28=0 27=1 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsth 31..29=0 28=0 27=0 26..25=1 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlsthu 31..29=0 28=0 27=1 26..25=1 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlstb 31..29=0 28=0 27=0 26..25=0 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vlstbu 31..29=0 28=0 27=1 26..25=0 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vflstd 31..29=0 28=1 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
-vflstw 31..29=0 28=1 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlstd 31..29=0 28=0 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlstw 31..29=0 28=0 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlstwu 31..29=0 28=0 27=1 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlsth 31..29=0 28=0 27=0 26..25=1 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlsthu 31..29=0 28=0 27=1 26..25=1 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlstb 31..29=0 28=0 27=0 26..25=0 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vlstbu 31..29=0 28=0 27=1 26..25=0 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vflstd 31..29=0 28=1 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
+@vflstw 31..29=0 28=1 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x16 1..0=3
# segment x/f s/u width xd xs1 xs2 opcode
# | | | | | | | |
-vsd 31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vsw 31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vsh 31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vsb 31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vfsd 31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
-vfsw 31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+@vsd 31..29=0 28=0 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+@vsw 31..29=0 28=0 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+@vsh 31..29=0 28=0 27=0 26..25=1 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+@vsb 31..29=0 28=0 27=0 26..25=0 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+@vfsd 31..29=0 28=1 27=0 26..25=3 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
+@vfsw 31..29=0 28=1 27=0 26..25=2 24..20=0 rs1 14=0 13=1 12=0 rd 6..2=0x1E 1..0=3
# segment x/f s/u width xd xs1 xs2 opcode
# | | | | | | | |
-vsstd 31..29=0 28=0 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vsstw 31..29=0 28=0 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vssth 31..29=0 28=0 27=0 26..25=1 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vsstb 31..29=0 28=0 27=0 26..25=0 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vfsstd 31..29=0 28=1 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
-vfsstw 31..29=0 28=1 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+@vsstd 31..29=0 28=0 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+@vsstw 31..29=0 28=0 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+@vssth 31..29=0 28=0 27=0 26..25=1 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+@vsstb 31..29=0 28=0 27=0 26..25=0 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+@vfsstd 31..29=0 28=1 27=0 26..25=3 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
+@vfsstw 31..29=0 28=1 27=0 26..25=2 rs2 rs1 14=0 13=1 12=1 rd 6..2=0x1E 1..0=3
diff --git a/opcodes-pseudo b/opcodes-pseudo
new file mode 100644
index 0000000..38a3887
--- /dev/null
+++ b/opcodes-pseudo
@@ -0,0 +1,10 @@
+# SYSTEM pseudo-instructions that map to csr*
+@fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3
+@frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
+@fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3
+@frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
+@fssr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3
+@frsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3
+@rdcycle rd 19..15=0 31..20=0x004 14..12=2 6..2=0x1C 1..0=3
+@rdtime rd 19..15=0 31..20=0x005 14..12=2 6..2=0x1C 1..0=3
+@rdinstret rd 19..15=0 31..20=0x006 14..12=2 6..2=0x1C 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 3117b8e..8b4b2ea 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -40,6 +40,35 @@ arglut['cimm6'] = (15,10)
arglut['cimm10'] = (14,5)
arglut['cimm5'] = (9,5)
+csrs = {
+ 0x001 : 'fflags',
+ 0x002 : 'frm',
+ 0x003 : 'fcsr',
+ 0x004 : 'cycle',
+ 0x005 : 'time',
+ 0x006 : 'instret',
+ 0x500 : 'sup0',
+ 0x501 : 'sup1',
+ 0x502 : 'epc',
+ 0x503 : 'badvaddr',
+ 0x504 : 'ptbr',
+ 0x505 : 'asid',
+ 0x506 : 'count',
+ 0x507 : 'compare',
+ 0x508 : 'evec',
+ 0x509 : 'cause',
+ 0x50A : 'status',
+ 0x50B : 'hartid',
+ 0x50C : 'impl',
+ 0x50D : 'fatc',
+ 0x50E : 'send_ipi',
+ 0x50F : 'clear_ipi',
+ 0x51C : 'stats', # XXX
+ 0x51D : 'reset',
+ 0x51E : 'tohost',
+ 0x51F : 'fromhost',
+}
+
opcode_base = 0
opcode_size = 7
funct_base = 12
@@ -49,17 +78,28 @@ def binary(n, digits=0):
rep = bin(n)[2:]
return rep if digits == 0 else ('0' * (digits - len(rep))) + rep
-def make_disasm_table(match,mask):
+def make_c(match,mask):
print '/* Automatically generated by parse-opcodes */'
- for name,match in match.iteritems():
+ print '#ifndef RISCV_ENCODING_H'
+ print '#define RISCV_ENCODING_H'
+ for name in match.iterkeys():
name2 = name.upper().replace('.','_')
- print '#define MATCH_%s %s' % (name2, hex(match))
- print '#define MASK_%s %s' % (name2, hex(mask[name]))
+ print '#define MATCH_%s %s' % (name2, hex(match[name]))
+ print '#define MASK_%s %s' % (name2, hex(mask[name]))
+ for num, name in csrs.items():
+ print '#define CSR_%s %s' % (name.upper(), hex(num))
+ print '#endif'
-def make_isasim(match, mask):
+ print '#ifdef DECLARE_INSN'
for name in match.iterkeys():
name2 = name.replace('.','_')
- print 'DECLARE_INSN(%s, 0x%x, 0x%x)' % (name2, match[name], mask[name])
+ print 'DECLARE_INSN(%s, MATCH_%s, MASK_%s)' % (name2, name2.upper(), name2.upper())
+ print '#endif'
+
+ print '#ifdef DECLARE_CSR'
+ for num, name in csrs.items():
+ print 'DECLARE_CSR(%s, CSR_%s)' % (name, name.upper())
+ print '#endif'
def yank(num,start,len):
return (num >> start) & ((1 << len) - 1)
@@ -490,7 +530,7 @@ def make_latex_table():
print_insts('addi', 'slti', 'sltiu', 'xori', 'ori', 'andi', 'slli', 'srli', 'srai')
print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and')
print_insts('fence', 'fence.i')
- print_insts('syscall', 'break', 'rdcycle', 'rdtime', 'rdinstret')
+ print_insts('scall', 'sbreak', 'rdcycle', 'rdtime', 'rdinstret')
print_footer(0)
print_header('r','a','i','s')
@@ -525,6 +565,8 @@ def make_latex_table():
print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s')
print_insts('feq.s', 'flt.s', 'fle.s')
print_insts('fssr', 'frsr')
+ print_insts('fsflags', 'frflags')
+ print_insts('fsrm', 'frrm')
print_footer(0)
print_header('r','r4','i','s')
@@ -555,9 +597,21 @@ def print_chisel_insn(name):
print s + "\")"
def make_chisel():
- print ' /* Automatically generated by parse-opcodes */'
+ print '/* Automatically generated by parse-opcodes */'
+ print 'object Instructions {'
for name in namelist:
print_chisel_insn(name)
+ print '}'
+ print 'object CSRs {'
+ for num, name in csrs.items():
+ print ' val %s = %d' % (name, num)
+ print ' val all = {'
+ print ' val res = collection.mutable.ArrayBuffer[Int]()'
+ for num, name in csrs.items():
+ print ' res += %s' % (name)
+ print ' res.toArray'
+ print ' }'
+ print '}'
for line in sys.stdin:
line = line.partition('#')
@@ -568,6 +622,9 @@ for line in sys.stdin:
assert len(tokens) >= 2
name = tokens[0]
+ pseudo = name[0] == '@'
+ if pseudo:
+ name = name[1:]
mymatch = 0
mymask = 0
cover = 0
@@ -610,9 +667,10 @@ for line in sys.stdin:
if not (cover == 0xFFFFFFFF or cover == 0xFFFF):
sys.exit("%s: not all bits are covered" % name)
- for name2,match2 in match.iteritems():
- if (match2 & mymask) == mymatch:
- sys.exit("%s and %s overlap" % (name,name2))
+ if not pseudo:
+ for name2,match2 in match.iteritems():
+ if (match2 & mymask) == mymatch:
+ sys.exit("%s and %s overlap" % (name,name2))
mask[name] = mymask
match[name] = mymatch
@@ -622,9 +680,7 @@ if sys.argv[1] == '-tex':
make_latex_table()
elif sys.argv[1] == '-chisel':
make_chisel()
-elif sys.argv[1] == '-disasm':
- make_disasm_table(match,mask)
-elif sys.argv[1] == '-isasim':
- make_isasim(match,mask)
+elif sys.argv[1] == '-c':
+ make_c(match,mask)
else:
assert 0