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authorYunsup Lee <yunsup@cs.berkeley.edu>2013-08-07 00:24:59 -0700
committerYunsup Lee <yunsup@cs.berkeley.edu>2013-08-07 00:25:52 -0700
commit503f720f5805fc787a70db9706f2048628210d38 (patch)
treedf57cf4c62049975576f362d48800250c046155d
parent1413f8f39d5f83c0b18a257d987a3e4973d045d7 (diff)
downloadriscv-opcodes-503f720f5805fc787a70db9706f2048628210d38.zip
riscv-opcodes-503f720f5805fc787a70db9706f2048628210d38.tar.gz
riscv-opcodes-503f720f5805fc787a70db9706f2048628210d38.tar.bz2
hwacha v3: inst format follows the new rocket accelerator extensions
-rw-r--r--opcodes-hwacha244
-rwxr-xr-xparse-opcodes2
2 files changed, 114 insertions, 132 deletions
diff --git a/opcodes-hwacha b/opcodes-hwacha
index 337523d..c8718b4 100644
--- a/opcodes-hwacha
+++ b/opcodes-hwacha
@@ -1,144 +1,124 @@
# vector scalar instructions
-stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3
-utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3
-movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3
-movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3
-fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3
-fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3
+stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=5 6..2=0x1D 1..0=3
+utidx rd 26..22=0 21..17=0 16..10=0 9..7=6 6..2=0x1D 1..0=3
+movz rd rs1 rs2 16..10=0 9..7=7 6..2=0x1D 1..0=3
+movn rd rs1 rs2 16..10=1 9..7=7 6..2=0x1D 1..0=3
+fmovz rd rs1 rs2 16..10=2 9..7=7 6..2=0x1D 1..0=3
+fmovn rd rs1 rs2 16..10=3 9..7=7 6..2=0x1D 1..0=3
-vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3
-vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3
-vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3
+# vector instructions
+vsetcfgvl rd rs1 rs2 acclimm7 9=1 8=1 7=1 6..2=0x02 1..0=3
+vsetvl rd rs1 21..17=0 16..10=0 9=1 8=1 7=0 6..2=0x02 1..0=3
+vmvv rd rs1 21..17=0 16..10=1 9=1 8=1 7=0 6..2=0x02 1..0=3
+vgetcfg rd 26..22=0 21..17=0 16..10=0 9=1 8=0 7=0 6..2=0x02 1..0=3
+vgetvl rd 26..22=0 21..17=0 16..10=1 9=1 8=0 7=0 6..2=0x02 1..0=3
+vf imm12hi rs1 21..17=0 imm12lo 9=0 8=1 7=0 6..2=0x02 1..0=3
-vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3
-vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3
-venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3
-venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3
-venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3
-venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3
+# vector supervisor instructions
+vxcptsave 31..27=0 rs1 21..17=0 16..10=0 9=0 8=1 7=1 6..2=0x02 1..0=3
+vxcptrestore 31..27=0 rs1 21..17=0 16..10=1 9=0 8=1 7=1 6..2=0x02 1..0=3
+vxcptkill 31..27=0 26..22=0 21..17=0 16..10=2 9=0 8=1 7=1 6..2=0x02 1..0=3
-# vector load mem instructions
+vxcptevac 31..27=0 rs1 21..17=0 16..10=3 9=0 8=1 7=1 6..2=0x02 1..0=3
+vxcpthold 31..27=0 26..22=0 21..17=0 16..10=4 9=0 8=1 7=1 6..2=0x02 1..0=3
+venqcmd 31..27=0 rs1 rs2 16..10=5 9=0 8=1 7=1 6..2=0x02 1..0=3
+venqimm1 31..27=0 rs1 rs2 16..10=6 9=0 8=1 7=1 6..2=0x02 1..0=3
+venqimm2 31..27=0 rs1 rs2 16..10=7 9=0 8=1 7=1 6..2=0x02 1..0=3
+venqcnt 31..27=0 rs1 rs2 16..10=8 9=0 8=1 7=1 6..2=0x02 1..0=3
-# 3=d
-# 2=seg 2=w
-# 1=st 1=seg 1=f 1=s 1=h
-# 0=u 0=etc 0=x 0=u 0=b
-# ----------------------------------------------------------------------------
-# mem padding type seg x/f u/s width opcode
-# unit stride | | | | | | | |
-# xloads | | | | | | | |
-vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+# 3=d
+# 2=w
+# 1=st 1=f 1=u 1=h 0 1 1=strided
+# 0=ld 0=x 0=s 0=b 0 1 0=unit-strided
+# ---------------------------------------------------
+# mem padding x/f u/s width xd xs1 xs2 opcode
+# unit-strided vector load | | | | | | | | |
+# | | | | | | | | |
+vld rd rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
+vlw rd rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
+vlwu rd rs1 21..17=0 16=0 15..14=0 13=0 12=1 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
+vlh rd rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x03 1..0=3
+vlhu rd rs1 21..17=0 16=0 15..14=0 13=0 12=1 11..10=1 9=0 8=1 7=0 6..2=0x03 1..0=3
+vlb rd rs1 21..17=0 16=0 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x03 1..0=3
+vlbu rd rs1 21..17=0 16=0 15..14=0 13=0 12=1 11..10=0 9=0 8=1 7=0 6..2=0x03 1..0=3
+vfld rd rs1 21..17=0 16=0 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
+vflw rd rs1 21..17=0 16=0 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
-# mem padding type seg x/f u/s width opcode
-# stride | | | | | | | |
-# xloads | | | | | | | |
-vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+# mem padding x/f u/s width xd xs1 xs2 opcode
+# strided vector load | | | | | | | | |
+# | | | | | | | | |
+vlstd rd rs1 rs2 16=0 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
+vlstw rd rs1 rs2 16=0 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
+vlstwu rd rs1 rs2 16=0 15..14=0 13=0 12=1 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
+vlsth rd rs1 rs2 16=0 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x03 1..0=3
+vlsthu rd rs1 rs2 16=0 15..14=0 13=0 12=1 11..10=1 9=0 8=1 7=1 6..2=0x03 1..0=3
+vlstb rd rs1 rs2 16=0 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x03 1..0=3
+vlstbu rd rs1 rs2 16=0 15..14=0 13=0 12=1 11..10=0 9=0 8=1 7=1 6..2=0x03 1..0=3
+vflstd rd rs1 rs2 16=0 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
+vflstw rd rs1 rs2 16=0 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
-# mem padding type seg x/f u/s width opcode
-# segment | | | | | | | |
-# xloads | | | | | | | |
-vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+# segment x/f u/s width xd xs1 xs2 opcode
+# segmented vector load | | | | | | | |
+# | | | | | | | |
+vlsegd rd rs1 21..17=0 vseglen 13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x16 1..0=3
+vlsegw rd rs1 21..17=0 vseglen 13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x16 1..0=3
+vlsegwu rd rs1 21..17=0 vseglen 13=0 12=1 11..10=2 9=0 8=1 7=0 6..2=0x16 1..0=3
+vlsegh rd rs1 21..17=0 vseglen 13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x16 1..0=3
+vlseghu rd rs1 21..17=0 vseglen 13=0 12=1 11..10=1 9=0 8=1 7=0 6..2=0x16 1..0=3
+vlsegb rd rs1 21..17=0 vseglen 13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x16 1..0=3
+vlsegbu rd rs1 21..17=0 vseglen 13=0 12=1 11..10=0 9=0 8=1 7=0 6..2=0x16 1..0=3
+vflsegd rd rs1 21..17=0 vseglen 13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x16 1..0=3
+vflsegw rd rs1 21..17=0 vseglen 13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x16 1..0=3
-# seg x/f u/s width opcode
-# stride segment | | | | |
-# xloads | | | | |
-vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3
-vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3
-vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3
-vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3
-vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3
-vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3
-vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3
-# floads
-vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3
-vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3
+# segment x/f u/s width xd xs1 xs2 opcode
+# segmented strided vector load | | | | | | | |
+# | | | | | | | |
+vlsegstd rd rs1 rs2 vseglen 13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x16 1..0=3
+vlsegstw rd rs1 rs2 vseglen 13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x16 1..0=3
+vlsegstwu rd rs1 rs2 vseglen 13=0 12=1 11..10=2 9=0 8=1 7=1 6..2=0x16 1..0=3
+vlsegsth rd rs1 rs2 vseglen 13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x16 1..0=3
+vlsegsthu rd rs1 rs2 vseglen 13=0 12=1 11..10=1 9=0 8=1 7=1 6..2=0x16 1..0=3
+vlsegstb rd rs1 rs2 vseglen 13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x16 1..0=3
+vlsegstbu rd rs1 rs2 vseglen 13=0 12=1 11..10=0 9=0 8=1 7=1 6..2=0x16 1..0=3
+vflsegstd rd rs1 21..17=0 vseglen 13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x16 1..0=3
+vflsegstw rd rs1 21..17=0 vseglen 13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x16 1..0=3
-# vector store mem instructions
-# mem padding type seg x/f u/s width opcode
-# unit stride | | | | | | | |
-# xstores | | | | | | | |
-vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+# mem padding x/f u/s width xd xs1 xs2 opcode
+# unit-strided vector store | | | | | | | | |
+# | | | | | | | | |
+vsd rd rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
+vsw rd rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
+vsh rd rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x03 1..0=3
+vsb rd rs1 21..17=0 16=1 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x03 1..0=3
+vfsd rd rs1 21..17=0 16=1 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x03 1..0=3
+vfsw rd rs1 21..17=0 16=1 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x03 1..0=3
-# mem padding type seg x/f u/s width opcode
-# stride | | | | | | | |
-# xstores | | | | | | | |
-vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+# mem padding x/f u/s width xd xs1 xs2 opcode
+# strided vector store | | | | | | | | |
+# | | | | | | | | |
+vsstd rd rs1 rs2 16=1 15..14=0 13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
+vsstw rd rs1 rs2 16=1 15..14=0 13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
+vssth rd rs1 rs2 16=1 15..14=0 13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x03 1..0=3
+vsstb rd rs1 rs2 16=1 15..14=0 13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x03 1..0=3
+vfsstd rd rs1 rs2 16=1 15..14=0 13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x03 1..0=3
+vfsstw rd rs1 rs2 16=1 15..14=0 13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x03 1..0=3
-# mem padding type seg x/f u/s width opcode
-# segment | | | | | | | |
-# xstores | | | | | | | |
-vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3
+# segment x/f u/s width xd xs1 xs2 opcode
+# segmented vector store | | | | | | | |
+# | | | | | | | |
+vssegd rd rs1 21..17=0 vseglen 13=0 12=0 11..10=3 9=0 8=1 7=0 6..2=0x1E 1..0=3
+vssegw rd rs1 21..17=0 vseglen 13=0 12=0 11..10=2 9=0 8=1 7=0 6..2=0x1E 1..0=3
+vssegh rd rs1 21..17=0 vseglen 13=0 12=0 11..10=1 9=0 8=1 7=0 6..2=0x1E 1..0=3
+vssegb rd rs1 21..17=0 vseglen 13=0 12=0 11..10=0 9=0 8=1 7=0 6..2=0x1E 1..0=3
+vfssegd rd rs1 21..17=0 vseglen 13=1 12=0 11..10=3 9=0 8=1 7=0 6..2=0x1E 1..0=3
+vfssegw rd rs1 21..17=0 vseglen 13=1 12=0 11..10=2 9=0 8=1 7=0 6..2=0x1E 1..0=3
-# seg x/f u/s width opcode
-# stride segment | | | | |
-# xstores | | | | |
-vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3
-vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3
-vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3
-vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3
-# fstores
-vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3
-vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3
-
-# other vector register instructions
-vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3
-vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3
-vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3
-vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3
-vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3
-vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3
-vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3
-vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3
-vvcfg 31..27=0 rs1 rs2 16..11=0 10..8=4 7=0 6..2=0x1C 1..0=3
-vtcfg 31..27=0 rs1 rs2 16..11=1 10..8=4 7=0 6..2=0x1C 1..0=3
-
-# other vector immediate instructions
-vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3
-vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3
-vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3
-vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3
+# segment x/f u/s width xd xs1 xs2 opcode
+# segmented strided vector store | | | | | | | |
+# | | | | | | | |
+vssegstd rd rs1 rs2 vseglen 13=0 12=0 11..10=3 9=0 8=1 7=1 6..2=0x1E 1..0=3
+vssegstw rd rs1 rs2 vseglen 13=0 12=0 11..10=2 9=0 8=1 7=1 6..2=0x1E 1..0=3
+vssegsth rd rs1 rs2 vseglen 13=0 12=0 11..10=1 9=0 8=1 7=1 6..2=0x1E 1..0=3
+vssegstb rd rs1 rs2 vseglen 13=0 12=0 11..10=0 9=0 8=1 7=1 6..2=0x1E 1..0=3
+vfssegstd rd rs1 21..17=0 vseglen 13=1 12=0 11..10=3 9=0 8=1 7=1 6..2=0x1E 1..0=3
+vfssegstw rd rs1 21..17=0 vseglen 13=1 12=0 11..10=2 9=0 8=1 7=1 6..2=0x1E 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 95785af..1132a3a 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -22,6 +22,8 @@ arglut['imm12hi'] = (31,27)
arglut['imm12lo'] = (16,10)
arglut['shamt'] = (15,10)
arglut['shamtw'] = (14,10)
+arglut['acclimm7'] = (16,10)
+arglut['vseglen'] = (16,14)
arglut['crd'] = (9,5)
arglut['crs2'] = (9,5)