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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-13 20:10:10 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-05-16 18:23:12 -0700 |
| commit | 61a642421d7f82abf874d56513158d652124f246 (patch) | |
| tree | 139ee99407dc607e6c686a008adf9a961f4176f3 /.gitignore | |
| parent | 73b3d3e819c341d76240365bc7c892fc686795fb (diff) | |
| download | riscv-opcodes-61a642421d7f82abf874d56513158d652124f246.zip riscv-opcodes-61a642421d7f82abf874d56513158d652124f246.tar.gz riscv-opcodes-61a642421d7f82abf874d56513158d652124f246.tar.bz2 | |
rvv: vector instruction encoding
add most of vector instruction encoding described in v-spec 0.7.
except for 'Zvamo' extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions