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| author | robinali-codasip <robin.ali@codasip.com> | 2025-12-04 00:22:01 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-12-03 16:22:01 -0800 |
| commit | 72b292677715a091a441c9a55f9d62715d3c5ba2 (patch) | |
| tree | 0b7a418878dcb1a96ad58bb17a48ed1675796a4c | |
| parent | 53c5af5dc41dd4a73a45c61bdb918d54b960e1e1 (diff) | |
| download | riscv-opcodes-master.zip riscv-opcodes-master.tar.gz riscv-opcodes-master.tar.bz2 | |
According to the RISC-V unprivileged spec, the following instructions
have a zero-extended immediate:
* vsll_vi
* vsrl_vi",
* vsra_vi
* vnsrl_wi
* vnsra_wi
* vssrl_vi
* vssra_vi
* vnclipu_wi
* vnclip_wi
* vslideup_vi
* vslidedown_vi
* vrgather_vi
| -rw-r--r-- | extensions/rv_v | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/extensions/rv_v b/extensions/rv_v index b40b860..69e42f8 100644 --- a/extensions/rv_v +++ b/extensions/rv_v @@ -308,9 +308,9 @@ vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrgather.vi 31..26=0x0c vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vslideup.vi 31..26=0x0e vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vslidedown.vi 31..26=0x0f vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 @@ -326,19 +326,19 @@ vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsll.vi 31..26=0x25 vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 -vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsrl.vi 31..26=0x28 vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vsra.vi 31..26=0x29 vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vssrl.vi 31..26=0x2a vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vssra.vi 31..26=0x2b vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vnsrl.wi 31..26=0x2c vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vnsra.wi 31..26=0x2d vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vnclipu.wi 31..26=0x2e vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 +vnclip.wi 31..26=0x2f vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 # OPMVV vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 |