Age | Commit message (Collapse) | Author | Files | Lines |
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Rvv pre 1.0
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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They aren't arch state
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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The original name misses the 'i' in instruction mae
vamoswape8 -> vamoswapei8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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The command parser still can accept SLEN but the value is not stored
in implementation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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some dump and comparison tool may depennd the initial state of
vector register.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Incorporate RVV 1.0 vtype layout change
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Some UCB implementations once used this to represent a pipeline bubble.
But this encoding is reserved for future standard HINT use.
Resolves #503
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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RISC-V H-Extension v0.6.1 Support
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It is very inconvenient to always embed kernel flat image into
OpenSBI for booting Linux/Xvisor on Spike.
We add optional "--kernel" command line option for spike. Using
this new option, users can specify kernel flat image separately
and OpenSBI ELF separately.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We add bootargs command-line option to Spike which allows us to
provide custom kernel parameters to Linux and Xvisor.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We add new HFENCE, HLV, and HSV instructions for HS-mode which
are defined as part of the RISC-V hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We extend our existing MMU implementation to support two-stage
translation when running VS-mode for RISC-V hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We add newly defined hypervisor CSRs and allow M/HS-mode to access
these CSRs. The MRET, SRET, ECALL and WFI instructions have also
been updated so that virt-to-novirt switch and exception cause is
based on HART virtualization state.
Subsequent patches will implement two-stage page tables, HFENCE
instructions and HSV/HLV instructions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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As section 3.6 says:
The vstart CSR is defined to have only enough writable bits to hold
the largest element index (one less than the maximum VLMAX) or lg2(VLEN) bits.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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With hypervisor extension, we have more CSRs providing trap
related information. We extend existing trap classes to pass
additional trap information required by hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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We add missing CSR and instruction encoding related defines
for hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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If n_pmp=0, then pmp is not implemented hence raise trap
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Commitlog 2020 07 02
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For csr register access instructions, there are log like
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Rvv fix 2020 06 25
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Rvv fix 2020 06 18
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Rvv fix 2020 06 17
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Extension zfh
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There are two options to specify custom extension and register it
1. --isa with x ex: --isa=rv64gcv_xmyext
parse, load, register in processor_t::processor_t
2. --extension
parse, load in main
register later by calling processort_t::register_extension
The patch fix the register pass in 2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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