index
:
riscv-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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2020-07-31
add configurable LR/SC reservation set
load_reservation_set_size
Udit Khanna
7
-11
/
+95
2020-07-30
Merge pull request #519 from chihminchao/rvv-pre-1.0
Andrew Waterman
64
-282
/
+483
2020-07-29
f16: fix Nan-Box macro
Chih-Min Chao
1
-1
/
+1
2020-07-29
rvv: fix frac_lmul get function
Chih-Min Chao
1
-1
/
+1
2020-07-29
rvv: remove isa string zvamoand zvlsseg
Chih-Min Chao
3
-18
/
+0
2020-07-29
rvv: remove veew/vemul state
Chih-Min Chao
3
-32
/
+25
2020-07-29
rvv: add vrgatherei16.vv
Chih-Min Chao
4
-13
/
+51
2020-07-29
rvv: add new whole reg load/store instructions
Chih-Min Chao
25
-23
/
+212
2020-07-29
rvv: op: rearrange some instruction since generation order change
Chih-Min Chao
1
-36
/
+36
2020-07-29
rvv: op: fix amo naming
Chih-Min Chao
39
-148
/
+148
2020-07-29
rvv: remove slen
Chih-Min Chao
2
-8
/
+5
2020-07-29
rvv: initialize vector register as zero
Chih-Min Chao
1
-1
/
+2
2020-07-29
rvv: disasm: fix missing vamoorei operands
Chih-Min Chao
1
-1
/
+2
2020-07-28
Merge pull request #517 from riscv/rvv-1.0-vtype
Andrew Waterman
2
-5
/
+4
2020-07-28
Incorporate RVV 1.0 vtype layout change
Andrew Waterman
2
-5
/
+4
2020-07-21
Remove deprecated decoding of xor x0,x0,x0
Andrew Waterman
1
-1
/
+0
2020-07-16
Fix legalize_privilege for extension H (#508)
Abhinay Kayastha
1
-1
/
+1
2020-07-15
commitlog: fix vmvnfr.v register information (#506)
Chih-Min Chao
1
-4
/
+17
2020-07-13
rvv: fix viota.m dst and src overlapping rule (#504)
Chih-Min Chao
1
-5
/
+1
2020-07-09
Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1
Andrew Waterman
35
-146
/
+946
2020-07-09
Add kernel command line option for spike
Anup Patel
1
-0
/
+18
2020-07-09
Add bootargs command-line option to Spike
Anup Patel
5
-8
/
+25
2020-07-09
Implement new instructions of hypervisor extension
Anup Patel
16
-0
/
+81
2020-07-09
Implement hypervisor two-stage MMU
Anup Patel
2
-51
/
+179
2020-07-09
Implement hypervisor CSRs read/write
Anup Patel
8
-53
/
+502
2020-07-08
rvv: vstart register needs only lg2(VLEN) bits (#501)
Chih-Min Chao
1
-1
/
+1
2020-07-08
Extend trap classes to pass more information
Anup Patel
7
-28
/
+60
2020-07-08
Add hypervisor extension related CSR and instruction defines
Anup Patel
1
-6
/
+81
2020-07-07
Merge pull request #500 from abhinay-kayastha/GetCsrZeroPmp
Udit Khanna
1
-0
/
+3
2020-07-06
If n_pmp=0, then pmp is not implemented hence raise trap
Abhinay Kayastha
1
-0
/
+3
2020-07-04
Merge pull request #499 from chihminchao/commitlog-2020-07-02
Andrew Waterman
5
-39
/
+142
2020-07-02
commitlog: support csr access
Chih-Min Chao
2
-2
/
+99
2020-07-02
commitlog: simplify print_value path
Chih-Min Chao
1
-26
/
+27
2020-07-02
commitlog: extend hint bit to record csr access
Chih-Min Chao
3
-6
/
+12
2020-07-02
rvv: make vmvfnr respect vstart
Chih-Min Chao
1
-5
/
+4
2020-06-25
Merge pull request #494 from chihminchao/rvv-fix-2020-06-25
Andrew Waterman
2
-4
/
+5
2020-06-25
rvv: remove unecessary access
Chih-Min Chao
1
-3
/
+0
2020-06-25
rvv: fix viota.m overlapping rule
Chih-Min Chao
1
-1
/
+5
2020-06-17
Merge pull request #491 from chihminchao/rvv-fix-2020-06-18
Andrew Waterman
3
-4
/
+4
2020-06-17
rvv: make v[sl]1r respect vstart
Chih-Min Chao
2
-2
/
+2
2020-06-17
rvv: commitlog: fix fractional lmul dump
Chih-Min Chao
1
-2
/
+2
2020-06-16
Merge pull request #490 from chihminchao/rvv-fix-2020-06-17
Andrew Waterman
3
-1
/
+11
2020-06-16
rvv: disasm: fix vwadd.wx operand
Chih-Min Chao
1
-1
/
+1
2020-06-16
zfh: support register dump in interactive mode
Chih-Min Chao
2
-0
/
+10
2020-06-16
Merge pull request #489 from chihminchao/extension-zfh
Andrew Waterman
40
-1
/
+357
2020-06-16
ext: handle diaseembler initialization from --extension
Chih-Min Chao
1
-0
/
+4
2020-06-16
zfh: implement all instructions
Chih-Min Chao
37
-1
/
+207
2020-06-16
zfh: disasm: add fp16 disasm
Chih-Min Chao
1
-0
/
+38
2020-06-16
zfh: op: add scalar opcode
Chih-Min Chao
1
-0
/
+108
2020-06-15
remove the redundant code (#488)
Dave Wen
2
-2
/
+1
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