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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-04 14:42:26 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-02-04 14:42:26 -0800 |
| commit | eb6586e3dea4a622bcdd4d518b25f8202b90eb40 (patch) | |
| tree | ddd70724a5a491f10fbfb39b55c976f739e2bed6 /softfloat | |
| parent | 98ccf030bb02a029944cd938d5bcb73275350df4 (diff) | |
| parent | aea74cb69437c1bb2f766e671b0d1b197aa51a6b (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind
Diffstat (limited to 'softfloat')
0 files changed, 0 insertions, 0 deletions